JPS6043592B2 - Large capacity static shift register - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a static shift register using a random access memory (hereinafter referred to as RAM) that has a large capacity and can provide an arbitrary number of shift stages.

Many conventional large-capacity shift registers operate dynamically, and most of them have a predetermined number of shift stages.

For this reason, conventional large-capacity shift registers can handle arbitrary shift registers. It was difficult to easily obtain the number of steps. Also R.A.
Conventional shift registers using M had the disadvantage of having too many components. This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by using an arbitrary number of RAMs, one ring counter, and the same number of flip-flops as RAMs, it has a large capacity and an arbitrary number. The purpose of the present invention is to provide a static shift register that can obtain a number of shift stages of . An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an example in which two stages of n-stage shift registers are connected.

In the figure, 11 is the first stage R into which data input a is input.
AM) 21 is a first stage flip-flop that temporarily stores the data output b of the first stage RAMII, and 12 is a second stage RAMN22 to which the latch data output of the first stage flip-flop 21 is input. data output b2
, and its latch data output C2 is used as the data output of the shift register. 3 counts the clock input d from o to (n-1) (n is a positive integer) and outputs it. 2 above using e as an address signal.
RAM II, 12 plus (n-1) ring counters. The clock signal d is input to the clock inputs of the first and second stage flip-flops 21 and 22, and is also input to the first and second stage RAM IIs and 12 as a read/write signal f. It is assumed that the flip-flops 21 and 22 latch data at the falling edge of the clock signal d.

Next, the operation will be explained.

Clock input d counts up (n-1) ring counter 3, and as shown by arrow A in FIG.
An address signal e is given to the MII, 12.

When the address signal e is input to RAM II, 12,
Clock input d is in “High” state and RA
Mll and l2 perform a read operation at the address specified by the address signal e. After the specified access time of RAMll, l2, as shown by arrow B, RAMl
Data outputs 1) 1, b2 of 1) 1, b2 appear, and these data outputs B1, b2 are taken into flip-flops 21, 22 by a clock signal d, as shown by arrow C.
At the time when the output data Bl, b2 of the RAMs 11, 12 are taken into the flip-flops 21, 22, the clock input d is in the state of ゜゜L0w゛, as shown by the subtitle D.
RAMll, l2 starts a write operation. Since the address signal e of RAMll, l2 does not change until the clock input d finishes changing from ゜"LOW゛ to ゜゜゜Hight1゛, RAMll, l2 writes data to the same address that was read. Then, the next clock When the signal d rises, the address signal e changes and the RAM address is updated, and the same operation as above is repeated with the updated address.When the above is repeated n times, RAM ll, l2 at the nth read Output data Bl, b2
It is clear that is the data written to R, AMll, l2 exactly n times ago. By repeating this operation, input data a is output with a delay of n bits for each stage of RAM1, and in this shift register in which two stages of RAM are connected, input data a is output with a delay of nod bits. In the above embodiment, the case where two stages of n-stage shift registers are connected has been described, but it goes without saying that the n-stage shift registers may be connected in arbitrary stages.

As described above, according to the large-capacity static shift register of the present invention, a large-capacity static shift register having an arbitrary number of stages can be achieved by using an arbitrary number of RAMs, one ring counter, and the same number of flip-flops as the RAMs. This has the effect of providing a shift register that is inexpensive and has a high degree of freedom.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of a large-capacity static shift register according to an embodiment of the present invention, and FIG. 2 is a diagram showing a time chart of signals of various parts in FIG. 11, 12...RAM, 21, 22...Flip-flop, 3...Ring counter, e...Address signal.

Claims (1)

[Claims] 1 Add an address signal to the first to mth stage random access memory (m is a positive integer) and the first to mth stage random access memory (n-1) Ring counter (n is a positive integer) and first to mth stage flip-flops that temporarily store the output data of the first to mth stage random access memories and use the latched output data as input to the next stage random access memory or output of the shift register. A large-capacity static shift register characterized by: