JPS6043593B2 - memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In a CCD memory device, two to four external terminals are used for CCD transfer locking, and one chip enable CE signal is also used.

However, when a total of 2 to 5 transfer lock c and chip enable CE signal terminals are required in this way, the number of clocks is large and complicated in terms of the mounting design of the memory device.

Therefore, it is an object of the present invention to provide a memory chip device that can internally generate a chip enable CE signal, thereby simplifying its packaging design.

According to one embodiment of the present invention, a transfer clock and an internal chip enable signal are generated based on a single phase input.

The internal chip enable signal generated based on the above-mentioned one-phase input, that is, the CCD register transfer lock c, and the chip supplied from the outside are connected to the input side of the circuit for generating clocks for address capture, data read, and data write. Logic circuit 1 receiving enable signal
is provided. By keeping the external chip enable CE signal at a DC-selected level, the CCD register transfer lock c allows address capture and Data
Each read and data write operation is controlled. As a result, if an external chip enable signal is present, the operation is controlled based on this external chip enable signal. According to this invention an external chip enable signal. If CE is not input, the CCD register transfer lock c can be used as is for inputting the chip enable CE signal as described above. That is, it becomes possible to generate a transfer lock with one clock input and perform each operation of address fetching, data reading, and data writing. FIG. 1 shows a circuit diagram of an embodiment of the present invention, and shows the logic configuration at the input portion of the CCD register transfer clock c and the external chip enable signal CE.

FIG. 2 is a signal waveform diagram in the circuit of FIG. 1. In Fig. 2, the external chip enable signal C is actually
Each signal waveform is shown when V is a DC level and the logical value is 0.

In addition, in FIG. 2, the dotted line indicates the delay waveform of the CCD register transfer clock 100. When the external chip enable signal C falls or rises during the period in which φC1 has a logic value of 0, φCIElO, φ ? ，
φ? It shows changes in each signal of φCICl and φCICl.

In FIG. 1, capacitors Cl, C2, C3, and C4 are
MOSFETQ2, Q5, Q8, Ql.

, when the source potential of Q2, Q5, Q8, Ql increases
By raising the gate potential of each of Q2, Q5, Q8, Ql. This is the bootstrap capacitance to ensure that the output voltage of VDD eventually reaches VDD. MOSFETQl, Q4, Q7
, Qll precharges Cl, C2, C3, and C4, and cuts off between this node and ■DD when the node connected to Cl, C2, C3, and C4 rises above the power supply voltage. It is. Q29Q59Q89
Ql2 is φCO, φ70, φ when the gate voltage of ~Q39Q69Q99 or QlO, Ql3 is O logic input.

EO,φ? This is a load MOSFET that raises the signal from a low potential to a DD potential. Q2 and Q3, Q5 and Q6, Q8
The constant ratios of the MOSs Q9, Q8 and QlO, and Ql2 and Ql3 are designed to ensure that each output potential is at the 0 logic level when the reference potential (earth potential) Vss side MOS is in a conductive state.

φ01 generation circuit 1, φ.

1 generation circuit 2, φCOl generation circuit 3, φ? The generation circuit 4 receives input signals φCO, φ70, and φCEO from the previous stage, respectively.
,φ? In response to the signal, φCl, φ correction, φCE,, φ...
generate a signal.

These circuits 1 to 4 are used as buffer circuits.
The φ1 generating circuit 5 receives the signal φC1 from the circuit 1 and outputs a clock signal φ1 which is at a high level for a certain period of time from approximately the rising edge of the signal φC1. The φ2 generating circuit 6 receives the signal φd from the circuit 2 and outputs a clock signal φ2 which is at a high level for a certain period of time from the rising edge of the signal φ2. The above φ and φ2 are two-phase clock signals related to the falling and rising edges of the input signal U. This two-phase clock signal is used as a transfer lock signal for the CCD register. With the configuration shown in Figure 1,
External chip enable belief? When the equipment is at the DC potential corresponding to the O logic input, φCEO maintains the O logic level until the internal chip enable signal φC1, which is the input of Q9, transitions from the logic level to the O logic level.

If the above signal maintains a 0 logic input, φCEO is φ. When 1 falls to the O logic level, it rises to the ■DD level (1 logic level), and conversely, when φ3 rises from the O logic level to the 1 logic level, it falls from the 1 logic level to the O logic level.

As shown by the broken line in FIG. 2, the external chip enable signal G is connected to the signal φ? When the signal C falls from the 1 logic level to the O logic level during a period when the signal C is at the O logic level, the signal φ.ICO changes as shown in the figure. φ acts as a delay and buffer.

. 1 generation circuit 8, and from this circuit 3 the signal φCE
l is output.

Output signal φ of the circuit 3 above.

E1 is supplied via an inverting circuit consisting of Qll to Ql3 and C4 to a φY generation circuit 4 which acts as a delay and a buffer, and this circuit 4 outputs an inverted signal.
The above φ.

Output signal φ of E1 generation circuit 3. E1 is supplied to an address capture circuit, a data read circuit, and a data write circuit (all not shown). The above address capture circuit,
The data read circuit and data write circuit use the signal φC
The operation is controlled by El. The address capture circuit, data read circuit, and data write circuit have, for example, a dynamic circuit configuration, and each circuit contact has a capacitor (
(not shown) is precharged.

The output signal φ of the φ... generation circuit 4 is used to control precharging of the seven address capture circuits, data read circuits, and data write circuits.

Precharging is performed when signal φ= is at 1 logic level, that is, before signal φCEO becomes 1 logic level. 9 The CCD memory device using the circuit shown in FIG. 1 above can be operated without supplying the chip enable signal C. FIG.
1 shows a block diagram of the chip enable terminals of two CCD memory devices M1, M2 each having a 1 data output terminal and a 0 logic input; FIG.

In the figure, by applying a transfer clock U, the CCD memory devices M1 and M2 transfer data in the CCD register, take in an address, read data, or write data. FIG. 4 shows a block diagram when an output signal from the control circuit CC is applied to the chip enable terminal CV.

In the figure, a control circuit CC receives a chip enable signal CH and a chip selection signal address signal ADI, and receives a chip enable signal CH and a chip selection signal address signal ADI.
A signal is output to enable the internal chip enable signal of the CCD memory device selected from among the CD memory devices M1 and M2. CC not selected by control circuit CC
In the D memory device, the CCD register is operated by a transfer lock U. In an unselected CCD memory device, the address capture circuit, data read circuit, data write circuit, etc. are configured such that the external chip enable signal is 1 when the internal chip enable signal is generated.
It does not work because it is at a logical level. As a result, it is possible to prevent the address capture circuit and the like in the unselected CCD memory device from consuming power unnecessarily. With the above configuration, the present invention applies a clock to only one of the CCD transfer lock and chip enable clocks, thereby controlling the CC of the CCD memory device.
D register transfer, address capture, data read or data write can be controlled.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an embodiment of the present invention.
The waveform diagram of each signal in the figure, and FIGS. 3 and 4 are block diagrams of the CCD memory device in use. C: Transfer lock terminal, C: Chip enable terminal, 1 to 6: Signal generation circuit.

Claims (1)

[Claims] 1. Timing signal generation means for forming a timing signal; receiving the timing signal formed by the timing signal generation means and a selection signal supplied via a signal terminal, and selecting the timing signal or chip; forming an internal chip selection signal in response to any one of the signals, wherein the operation of the address capture circuit is controlled based on the internal chip selection signal. A memory device having means for. 2. The chip selection signal is maintained in a state selecting a memory device, thereby causing the means to form an internal chip selection signal in response to the timing signal. A memory device having means for forming an internal chip select signal.