JPS6045045A - Multilayer ceramic package - Google Patents
Multilayer ceramic packageInfo
- Publication number
- JPS6045045A JPS6045045A JP58153628A JP15362883A JPS6045045A JP S6045045 A JPS6045045 A JP S6045045A JP 58153628 A JP58153628 A JP 58153628A JP 15362883 A JP15362883 A JP 15362883A JP S6045045 A JPS6045045 A JP S6045045A
- Authority
- JP
- Japan
- Prior art keywords
- internal wiring
- substrate
- conductive
- wall
- led out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
＋ａ＋ 発明の技術分野
本発明は半導体素子等を収容するための多層セラミック
パッケージに係り、特に内部配線の構成に関する。DETAILED DESCRIPTION OF THE INVENTION +a+ Technical Field of the Invention The present invention relates to a multilayer ceramic package for accommodating semiconductor elements and the like, and particularly to the structure of internal wiring.
（ｂｌ 従来技術と問題点
近年に至り集積回路装置がＬＳＩ、ＶＬＳＩと集積度が
増大するにつれて、そのパターンはまずます微細化、高
密度化する状況にある。 これに伴って半導体素子を収
容するパッケージに設けられた外部端子数及びボンディ
ングバソド数が増大し、そのためこの両者間を連結する
内部配線パターンも微細化且つ高密度化せざるを得ない
。(bl) Prior Art and Problems In recent years, as the degree of integration of integrated circuit devices has increased from LSI to VLSI, their patterns have become increasingly finer and denser. As the number of external terminals and the number of bonding baths provided in a package increases, the internal wiring patterns connecting these terminals must also become finer and more dense.
上記内部配線は抵抗値が低いことを要するが、上述のよ
うにパターンが微細化するとその抵抗値を低く押さえる
ことが困難となる。The internal wiring is required to have a low resistance value, but as the pattern becomes finer as described above, it becomes difficult to keep the resistance value low.
（Ｃ１発明の目的
本発明の目的は上記問題点を解消して、内部配線の抵抗
値を低くし得る改良されゾこ構造の多層セラミックパッ
ケージを提供することにある。(C1 Object of the Invention The object of the present invention is to solve the above-mentioned problems and provide an improved multilayer ceramic package with a zigzag structure capable of lowering the resistance value of internal wiring.
（ｄ＋ 発明の構成
本発明の特徴は、複数層のセラミック基板が積層されて
なり、内部に半導体素子を搭載するための凹部を有する
とともに、前記複数層のセラミノり基板のうちの所定層
のセラミック基板の前記四部周縁部に、前記四部に搭載
せる半導体素子より導出された導電配線を接続するため
のボンディングバンドが複数個配設されてなり、且つ該
ボンディングバンドから内部配線を介して導出された複
数個の外部端子を具備する構成において、前記内部配線
の少なくとも一部が対応するボンディングバンドから前
記凹部側壁面上を経て対応する外部端子−に導出された
ことにある。(d+ Structure of the Invention The present invention is characterized by a plurality of laminated ceramic substrates, each having a recessed portion for mounting a semiconductor element therein, and a predetermined ceramic layer of the plurality of ceramic substrates). A plurality of bonding bands are disposed on the periphery of the four parts of the substrate for connecting conductive wires led out from the semiconductor elements mounted on the four parts, and the conductive wires are led out from the bonding bands via internal wires. In the configuration including a plurality of external terminals, at least a part of the internal wiring is led out from the corresponding bonding band to the corresponding external terminal via the side wall surface of the recess.
（ｅｌ 発明の実施例
従来の多層セラミックパッケージの構造は第１図＋ａ＋
〜（Ｃ１に示すように、半導体素子を固着するためのラ
ンド４を有するダイアタッチ基板１と、半導体素子の各
電極から導出されたアルミニウム（八〇）細線のような
金属細線をボンディングするボンディングバンド５と、
該ボンディングバンド５と外部端子を構成する導電層８
とを連結するための内部配線６が設りられた内部配線形
成基板２と、その」二層に配設され、キャンプ（図示せ
ず）を固着するための１１止用基板３等から構成されて
いる。(el Embodiment of the Invention The structure of a conventional multilayer ceramic package is shown in Figure 1+a+
~ (As shown in C1, a die attach substrate 1 having lands 4 for fixing a semiconductor element, and a bonding band for bonding thin metal wires such as aluminum (80) thin wires derived from each electrode of the semiconductor element. 5 and
A conductive layer 8 constituting the bonding band 5 and an external terminal.
It consists of an internal wiring forming board 2 on which internal wiring 6 is provided for connecting the two, and an 11 stop board 3, etc., which is arranged in two layers and is used to fix a camp (not shown). ing.
なおダイアタッチ基板１．内ｉ（１；配線形成基板２゜
及び封止用基板３それぞれの側壁部に設けられた外壁導
電層７，８．９は、パッケージ完成時には相互に連結さ
れ、図示はしていないがダイアタッチ基板１裏面に形成
された端子バソ１のような外部端子に接続される。Note that die attach substrate 1. Inner i(1; Outer wall conductive layers 7, 8.9 provided on the respective side walls of the wiring forming substrate 2° and the sealing substrate 3 are connected to each other when the package is completed, and die attaching is performed (not shown). It is connected to an external terminal such as a terminal base 1 formed on the back surface of the substrate 1.
上記内部配線６はすべて内部配線基板２十に形成されて
いるが、前述した如く昨今の超大規模集積回路装置（Ｖ
ＬＳＩ）においてし才、外部醋１子の数が１００本を越
えるものもある。従ってかかる半導体装置用として用い
られるパッケージでは、内部配線６は僅か１０ （ｍｍ
）程の幅の中に３０木以」二も配設されることとなる。All of the internal wiring 6 is formed on the internal wiring board 20, but as mentioned above, in recent ultra-large scale integrated circuit devices (V
LSI), some have more than 100 foreigners. Therefore, in a package used for such a semiconductor device, the internal wiring 6 is only 10 (mm
), more than 30 trees will be placed within a width of about 300 meters.
そのため内部配線６の太さは極めて細いものとなり、そ
の抵抗値が増大せざるを得ない。Therefore, the thickness of the internal wiring 6 becomes extremely thin, and its resistance value inevitably increases.
本発明はかかる問題点を解消するためになされたもので
、第２図の斜視図に示す如く、内部配線形成基板２を複
数層（本実施例で（ｊ第１．第２゜第３の３Ｍの内部配
線層２１．２２．２３）をもって構成し、各層にそれぞ
れ内部配線をう〕割形成したごとにより、線幅の広い内
部配線を形成可能とし、該内部配線の抵抗値を低減した
ものである。The present invention has been made to solve this problem, and as shown in the perspective view of FIG. 3M's internal wiring layer 21, 22, 23), and by forming internal wiring in each layer, it is possible to form internal wiring with a wide line width, and the resistance value of the internal wiring is reduced. It is.
以下本発明の一実施例を第２図を参照しながら具体的に
説明する。An embodiment of the present invention will be specifically described below with reference to FIG.
即し本実施例においては内部配線形成基板２を第１〜第
３の３１ｉｉ５の基板２１〜２３をもって構成し、ボン
ディングバソｌ”５１．５２．５３・・・は中央に位置
する第２の内部配線基板２１上に総て配設する。これら
多数のポンディングパッド５１．５２．５３．・・・の
うちの一部３例えばポンディングパツド５２は当該基板
２１上に直接形成された導電配線６２．・・・を介して
、外壁導電Ｊｉ８２−２に導出され、また他の一部１例
えば５１．５３は当該基板２１或いは上層の基板２２の
貫通孔内壁面上に形成された内壁導電層９１，９３．・
・・、並びに上層または下層の基板２２．２３表面に形
成された導電配線６１．６３．・・・を介して、それぞ
れ側壁面上に形成された外壁導電Ｐ８２４．８２−３．
・・・に導出されている。That is, in this embodiment, the internal wiring forming board 2 is composed of the first to third 31ii5 boards 21 to 23, and the bonding baths l"51, 52, 53... All of them are arranged on the wiring board 21. Some of these many bonding pads 51, 52, 53, etc., for example, the bonding pads 52 are conductive wirings formed directly on the board 21. The other part 1, for example 51.53, is an inner wall conductive layer formed on the inner wall surface of the through hole of the substrate 21 or the upper substrate 22. 91,93.・
. . . and conductive wirings 61, 63, . . . formed on the surface of the upper or lower substrate 22, 23. . . , the outer wall conductors P824, 82-3, .
... has been derived.
そし゛ζ上記各基板１ 、２１．２２．２３の側壁面上
に形成された外壁導電層８１−１．２，３．４等は総て
相互に連結され、ダイアタッチ基板１裏面に設けられた
外部端子（図示せず）に接続される。Then, the outer wall conductive layers 81-1.2, 3.4, etc. formed on the side walls of the respective substrates 1, 21, 22, 23 are all interconnected, and the outer wall conductive layers 81-1.2, 3.4, etc. formed on the back surface of the die attach substrate 1 are connected to an external terminal (not shown).
このように本実施例の内部配線６は、ポンディングパツ
ド５１．・・・と、内壁導電１ｉ９１．・・・と、導電
配線６１．・・・とから構成される。かかる内部配線を
従来のものと比較すると、導電配線６１．・・・ＵＪ従
来より２〜４倍の幅とすることが出来るので、その抵抗
値は大幅に低下するが、内壁導電１皆９１．・・・は本
実施例で新たに設けられノこものであって、これの抵抗
値は内部配線６の抵抗値を増大させる要素となる。しか
しながらこの内壁導電ｆｆ１９１．・・・は、各基板］
、、 ２１．２２．２３． ３を積層焼成した後に施さ
れるメッキ工程において、表面に金（Ａｕ）のような高
導電率の金属がメッキされる。従ってこの内壁導電Ｊｆ
ｉｔ９１．・・・を設けたことによる抵抗値の増大は殆
ど問題にならない。In this way, the internal wiring 6 of this embodiment is connected to the bonding pads 51 . ...and inner wall conductivity 1i91. ...and conductive wiring 61. It consists of... Comparing such internal wiring with conventional ones, the conductive wiring 61. ...Since the width can be made 2 to 4 times larger than that of the conventional UJ, the resistance value is significantly lowered, but the inner wall conductivity 1 is 91. . . . are newly provided in this embodiment, and the resistance value thereof becomes an element that increases the resistance value of the internal wiring 6. However, this inner wall conductivity ff191. ... is each board]
,, 21.22.23. In the plating step performed after laminating and firing 3, the surface is plated with a highly conductive metal such as gold (Au). Therefore, this inner wall conductivity Jf
it91. The increase in resistance value due to the provision of ... hardly poses a problem.
このことは本実施例におりる最悪条件の内部配線の抵抗
値が、凡そ２５２（ｍΩＪであるのに幻して、従来の平
均的な内部配線の抵抗（ｉＮが凡そ５６７〔ｍΩ〕であ
ることからも容易に理解されよう。This means that the resistance value of the internal wiring under the worst condition in this example is approximately 252 (mΩJ), whereas the resistance value of the conventional average internal wiring (iN is approximately 567 [mΩ]). It can be easily understood from this.
なお」二記本実施例の内部配線の各部の寸法は、ボンデ
ィングパノド５１の幅、長さがそれぞれ約０．２（ｍｍ
） 、３．０ （＋ｎｍ） 、内壁導電Ｊｉｉｆ９１の
幅及び長さが凡そ０．１ （ｍｍ） 、 ０．４ （ｍ
ｍ〕、導電配線６１の幅及び区さが凡そ０．６ （ｍｍ
） 、 １０．０ （ｍｍ３である。Note that the dimensions of each part of the internal wiring in this embodiment are such that the width and length of the bonding panod 51 are approximately 0.2 (mm), respectively.
), 3.0 (+nm), and the width and length of the inner wall conductive Jiif91 are approximately 0.1 (mm), 0.4 (m
m], the width and division of the conductive wiring 61 is approximately 0.6 (mm)
), 10.0 (mm3).
これに対し、従来例の内部配線の各部の寸法は、ボンデ
ィングパソド５の各部は上記本実施例と変わるところは
なく、内部配線６の幅及び長さがそれぞれ凡そ０．２〔
ｍｍ） 、３．０ （ｍｍ）である。On the other hand, the dimensions of each part of the internal wiring in the conventional example are the same as those in this embodiment described above for each part of the bonding path 5, and the width and length of the internal wiring 6 are approximately 0.2 [
mm), 3.0 (mm).
」二連の如く構成した本発明の一実施例では、内部配線
形成基板２を複数個の基板により構成し、導電配線をこ
の複数個の基板上に分割して形成したことにより、内部
配線の抵抗値を著しく減少させることが出来た。In one embodiment of the present invention, which is configured as a double series, the internal wiring forming board 2 is composed of a plurality of substrates, and the conductive wiring is divided and formed on the plurality of substrates. It was possible to significantly reduce the resistance value.
なお上記一実施例ではデュアル・イン・ライン（ＤＩＰ
）型の多層セラミックパッケージを掲げて説明したが、
本発明はこれに限定されるものではなく、如何なる型の
多層セラミックパッケージの作成にも用いることが出来
る。Note that in the above embodiment, dual in line (DIP)
) type multilayer ceramic package was explained.
The invention is not limited thereto and can be used to create any type of multilayer ceramic package.
（Ｔｌ 発明の詳細
な説明した如く本発明によれば、内部配線の抵抗値の低
い、改良された構造の多層セラミックパッケージが得ら
れる。(Tl) As described in detail, according to the present invention, a multilayer ceramic package with an improved structure in which the internal wiring has a low resistance value can be obtained.
第１図は従来の多層セラミックパッケージの説明に供す
るための分解斜視図、第２図は本発明の一実施例の構成
を示す分解斜視図である。
図において、１はダイアタッチ基板、２．２＋。
２２．２３．・・・は内部配線形成基板、３は封止用基
板、４はランド、５．５１．５２．５３．・・・はボン
ディングパソド、６は内部配線、６１．６２．６３．・
・・は導電配線、７．８．９及び８１，８２．・・・は
外壁導電層、９１゜９３、・・・は内壁導電層を示す。
第１図
４Ｇ）
第２０FIG. 1 is an exploded perspective view for explaining a conventional multilayer ceramic package, and FIG. 2 is an exploded perspective view showing the configuration of an embodiment of the present invention. In the figure, 1 is a die attach substrate, 2.2+. 22.23. . . . is an internal wiring forming substrate, 3 is a sealing substrate, 4 is a land, 5.51.52.53. . . . is a bonding pad, 6 is an internal wiring, 61.62.63.・
... is conductive wiring, 7.8.9 and 81, 82. . . . indicates an outer wall conductive layer, and 91°, 93, . . . indicate an inner wall conductive layer. Figure 1 4G) 20th
Claims (1)
体素子を搭載するための四部を有するとともに、前記複
数層のセラミック基板のうちの所定層のセラミック基板
の前記凹部周縁部に、前記四部に搭載せる半導体素子よ
り導出された導電配線を接続するためのポンディングパ
ッドが複数個配設されてなり、且つ該ポンディングパッ
ドから内部配線を介して導出された複数個の外部端子を
具備する構成において、前記内部配線の少なくとも一部
が対応するポンディングパッドから前記凹部側壁面上を
経て対応する外部端子に導出されたことを特徴とする多
層セラミックパッケージ。A plurality of layers of ceramic substrates are stacked, each having four parts for mounting a semiconductor element therein, and the four parts are mounted on the periphery of the recess of a predetermined layer of the ceramic substrate of the plurality of layers of ceramic substrates. In a structure in which a plurality of bonding pads are arranged for connecting conductive wiring led out from a semiconductor element that is connected to the semiconductor device, and a plurality of external terminals are led out from the bonding pads via internal wiring. . A multilayer ceramic package, wherein at least a part of the internal wiring is led out from a corresponding bonding pad to a corresponding external terminal via a side wall surface of the recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58153628A JPS6045045A (en) | 1983-08-23 | 1983-08-23 | Multilayer ceramic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58153628A JPS6045045A (en) | 1983-08-23 | 1983-08-23 | Multilayer ceramic package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6045045A true JPS6045045A (en) | 1985-03-11 |
| JPH0478014B2 JPH0478014B2 (en) | 1992-12-10 |
Family
ID=15566655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58153628A Granted JPS6045045A (en) | 1983-08-23 | 1983-08-23 | Multilayer ceramic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6045045A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05267497A (en) * | 1992-03-23 | 1993-10-15 | Japan Radio Co Ltd | Electronic component package |
| JPH065067U (en) * | 1992-06-22 | 1994-01-21 | 日本航空電子工業株式会社 | Illuminated integrated key top |
| CN109411365A (en) * | 2016-07-17 | 2019-03-01 | 高锦 | A kind of packaging method for the stacked integrated circuit encapsulating structure preventing bending warpage |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4911575A (en) * | 1972-06-01 | 1974-02-01 | ||
| JPS511392A (en) * | 1974-06-14 | 1976-01-08 | Mitsubishi Kakoki Kk | ARYUSANGASUGANJUGASUKARAIONOSEIZOHOHO |
| JPS5213772A (en) * | 1975-07-22 | 1977-02-02 | Kyocera Corp | Ic package |
| JPS5254963A (en) * | 1975-10-31 | 1977-05-04 | Nippon Electric Co | Circuit substrate having metalized wiring layer |
| JPS5822741U (en) * | 1981-08-07 | 1983-02-12 | 京セラ株式会社 | semiconductor package |
| JPS58122459U (en) * | 1982-02-15 | 1983-08-20 | 株式会社東芝 | Semiconductor device envelope |
| JPS58197861A (en) * | 1982-05-14 | 1983-11-17 | Nec Corp | Ceramic substrate and manufacture thereof |
-
1983
- 1983-08-23 JP JP58153628A patent/JPS6045045A/en active Granted
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4911575A (en) * | 1972-06-01 | 1974-02-01 | ||
| JPS511392A (en) * | 1974-06-14 | 1976-01-08 | Mitsubishi Kakoki Kk | ARYUSANGASUGANJUGASUKARAIONOSEIZOHOHO |
| JPS5213772A (en) * | 1975-07-22 | 1977-02-02 | Kyocera Corp | Ic package |
| JPS5254963A (en) * | 1975-10-31 | 1977-05-04 | Nippon Electric Co | Circuit substrate having metalized wiring layer |
| JPS5822741U (en) * | 1981-08-07 | 1983-02-12 | 京セラ株式会社 | semiconductor package |
| JPS58122459U (en) * | 1982-02-15 | 1983-08-20 | 株式会社東芝 | Semiconductor device envelope |
| JPS58197861A (en) * | 1982-05-14 | 1983-11-17 | Nec Corp | Ceramic substrate and manufacture thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05267497A (en) * | 1992-03-23 | 1993-10-15 | Japan Radio Co Ltd | Electronic component package |
| JPH065067U (en) * | 1992-06-22 | 1994-01-21 | 日本航空電子工業株式会社 | Illuminated integrated key top |
| CN109411365A (en) * | 2016-07-17 | 2019-03-01 | 高锦 | A kind of packaging method for the stacked integrated circuit encapsulating structure preventing bending warpage |
| CN109411361A (en) * | 2016-07-17 | 2019-03-01 | 高锦 | A kind of packaging method of stacked integrated circuit encapsulating structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0478014B2 (en) | 1992-12-10 |
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