JPS6045494U - 混成集積回路装置 - Google Patents

混成集積回路装置

Info

Publication number
JPS6045494U
JPS6045494U JP1983138195U JP13819583U JPS6045494U JP S6045494 U JPS6045494 U JP S6045494U JP 1983138195 U JP1983138195 U JP 1983138195U JP 13819583 U JP13819583 U JP 13819583U JP S6045494 U JPS6045494 U JP S6045494U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
hybrid integrated
heat dissipation
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983138195U
Other languages
English (en)
Inventor
田島　恒宗
冨居　壱城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP1983138195U priority Critical patent/JPS6045494U/ja
Publication of JPS6045494U publication Critical patent/JPS6045494U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H10W72/01515—Forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/381—Auxiliary members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来の混成集積回路装置の１例を示す断面図、
第２図は本考案の１実施例を示す断面図、第３゛図及び
第４図は他の実施例を示す断面図である。 １．２１は混成集積回路装置、４，３３は配線基板、５
は半導体素子、６は電子部品、７はケース、２２は放熱
板、２３は放熱基板、２５は半導体装置である。

Claims (1)

  1. 【実用新案登録請求の範囲】 １　放熱面を一方の面に有してモールドされた半導体装
    置と他の電子部品と配線基板を備え、上記半導体装置が
    上記放熱面を外部に開放した状態で一体に構成されてい
    ることを特徴とする混成集積回路装置。 ２　複数の半導体装置の放熱面が配線基板の面と平行で
    あり、且つ同一面に配されていることを特徴とする実用
    新案登録請求の範囲第１項記載の混成集積回路装置。 ３　複数の半導体装置が基板に対して左右又は上下のい
    ずれかについて略対称に配されていることを特徴とする
    実用新案登録請求の範囲第１項又は第２項記載の混成集
    積回路装置。
JP1983138195U 1983-09-06 1983-09-06 混成集積回路装置 Pending JPS6045494U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983138195U JPS6045494U (ja) 1983-09-06 1983-09-06 混成集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983138195U JPS6045494U (ja) 1983-09-06 1983-09-06 混成集積回路装置

Publications (1)

Publication Number Publication Date
JPS6045494U true JPS6045494U (ja) 1985-03-30

Family

ID=30310158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983138195U Pending JPS6045494U (ja) 1983-09-06 1983-09-06 混成集積回路装置

Country Status (1)

Country Link
JP (1) JPS6045494U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017154075A1 (ja) * 2016-03-07 2017-09-14 三菱電機株式会社 電子制御装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017154075A1 (ja) * 2016-03-07 2017-09-14 三菱電機株式会社 電子制御装置
JPWO2017154075A1 (ja) * 2016-03-07 2018-05-24 三菱電機株式会社 電子制御装置
US10548213B2 (en) 2016-03-07 2020-01-28 Mitsubishi Electric Corporation Electronic controlling apparatus

Similar Documents

Publication Publication Date Title
JPS58188684U (ja) 電子表示装置
JPS6045494U (ja) 混成集積回路装置
JPS58122461U (ja) 実装基板
JPS5937742U (ja) 放熱構造
JPS602841U (ja) 半導体取付基板
JPS6090844U (ja) 混成集積回路装置
JPS6090843U (ja) Ｉｃなどの放熱装置
JPS59159954U (ja) プリント基板用放熱装置
JPS59140446U (ja) 混成集積回路用パツケ−ジ
JPS6045447U (ja) 半導体装置
JPS6049662U (ja) チップ部品の実装構造
JPS6052629U (ja) 混成集積回路装置
JPS5846456U (ja) 放熱体の取付構造
JPS58182435U (ja) 半導体素子の外付け端子構造
JPS594646U (ja) 放熱板の取付装置
JPS5952641U (ja) 半導体パツケ−ジの放熱装置
JPS6078142U (ja) 集積回路装置
JPS6113994U (ja) 電子装置
JPS59155758U (ja) 印刷配線板
JPS59143050U (ja) 半導体装置
JPS5999477U (ja) 混成集積回路装置
JPS6081674U (ja) セラミツク混成集積回路装置
JPS59131192U (ja) トランジスタ回路の実装構造
JPS5860993U (ja) 電子部品用放熱板
JPS5956751U (ja) 電源バス