JPS604636B2 - color imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color imaging device that adjusts the white balance of a video signal sent from an imaging device within a certain period of time and automatically maintains the white balance.

Generally, when a white screen is to be photographed in a color imaging device, white balance is achieved by equalizing the signal levels obtained from the red, green, and blue signal systems.

Since it takes a very long time to adjust this, it has been proposed in the past to automatically adjust the white balance by turning on and off a switch, as shown in FIG. In Fig. 1, 1 indicates the camera head and the process section, and the red, green, and
Supplying a green signal to the encoder 5 through each transmission path,
I am getting a standard color television signal. In this follow-up example, gain control circuits 6a and 6b are provided for the red signal and green signal transmission lines, and these gain control circuits 6a,
Memory circuits 7a and 7b are provided for supplying a control signal to 6b and holding the state thereof. In this case, memory circuits 7a, 7b
In this case, comparison outputs of color signals are combined from comparison and subtraction circuits 8a and 8b including rectifier circuits through mutually interlocking manual switches S and S2. That is, a comparison output between a red signal and a green signal is supplied to the memory circuit 7a provided on the red signal system side, and a comparison output between a blue signal and a green signal is supplied to the memory circuit 7a provided on the blue signal system side. is being done. Therefore, by turning on the switches S, , S2, a negative feedback loop is formed, which works so that the outputs of the gain control circuits 6a, 6b and the green level are equal, and after the switches S, , S2 are turned off, The control voltage immediately before turning off is stored in the memory circuits 7a and 7b.
is maintained, and the gain control circuits 6a and 6b are operated respectively, so that it is possible to take pictures with a well-balanced white state. Note that the memory circuits 7a and 7b are composed of a MOSFET 9, a resistor 10, and a capacitor 11, as shown in FIG.

The storage circuits 7a and 7b utilize the high input impedance of the MOSFET 9 to accumulate and store charges in the capacitor 1. However, these memory circuits 7a, 7
In b, the lead wires between the switches S, S2 and the memory circuits 7a, 7b, the MOSFET 9, and the exposed part of the capacitor 11 are connected to the second relay using a reed relay 12 to discharge the charge accumulated in the capacitor 11 due to moisture. Figure - The part indicated by the dotted chain line is molded with resin. In this method as well, MO
Since the input impedance of SFET 9 is limited, the charge in capacitor 11 will be discharged after a long period of time. As is clear from the above description, the conventional apparatus uses a reed relay, making the apparatus large, making it impossible to store information for a long time, and making it impossible to determine whether or not the white balance has been adjusted.

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, to make the storage time infinite, and to provide a circuit configuration that can be miniaturized.

Embodiments of the present invention will be described in detail below with reference to FIG.

3 are the same as those in FIG. 1, and red, green, and blue signals with white balance are supplied to the encoder 5 through respective signal transmission paths. . In this embodiment, gain control circuits 13a and 1 are provided for red and blue signal systems, respectively.
3b is provided, the gain is controlled by the output of the DA converters 14a, 14b, and the output of the gain control circuits 13a, 13b is compared with the level of the green signal by increase/decrease discrimination circuits 15a, 15b, respectively, and the reversible counting circuits 16a, 16b, and uses the output signals of the increase/decrease discrimination circuits 15a, 15b to convert the reversible counting circuits 16a, 16b configured with digital circuits.
The reversible counting circuit 16
The count outputs of a and 16b are DA-converted by a DA converter and added as control signals to the control signals of gain control circuits 13a and 13b. . However, the pulse generating circuit is constructed so that a clock pulse is generated by a start pulse, and when the number of pulses reaches a predetermined number, the clock pulse disappears. Next, the operation of this embodiment will be explained.

Now, if the increase and decrease of the reversible counting circuits 16a and 16b and the increase and decrease of the gain of the gain control circuits 13a and 13b are made in the same direction, the levels of the red and blue signals supplied to terminals 2 and 4 are the same as the level of the green signal supplied to terminal 3. If the level of the red and blue signals supplied to the terminals 2 and 4 is smaller than that of the green signal supplied to the terminal 3, the increase/decrease judgment circuits 15a and 15b output a signal for increasing the reversible counting circuits 16a and 16b, and the level of the red and blue signals supplied to the terminals 2 and 4 becomes the green signal supplied to the terminal 3 If it is larger than the signal level, the increase/decrease discrimination circuits 15a, 15b output a signal that causes the reversible counting circuits 16a, 16b to decrease. When a start pulse is applied to the pulse generation circuit 17 in this state, a clock pulse for driving the reversible counting circuits 13a and 13b is generated. Increase/decrease determination circuit 16a
, 15b, the reversible counting circuits 13a, 13b are controlled to increase or decrease, and the count value changes, and the levels of the red and blue signals and the green signal entering the encoder 5 rise and fall in synchronization with the clock pulse. There is a place. In synchronization with this up and down, the reversible counting circuits 16a and 16b repeat binary counts. A state in which these two values are repeated indicates a state in which the white balance is approximately balanced. Here, pulse generation circuit 1
7 generates a predetermined number of pulses. Since there is no clock pulse, the reversible counting circuits 16a and 16b
As counting, one of the above two-value repetition is stopped, and the count outputs of the reversible counting circuits 16a and 16b at this stop are DA-converted by DA converters 14a and 14b and used as control signals in gain control circuits 13a and 13b. In addition, the levels of red, blue, and green signals are made equal. When the change in the level of the red and blue signals is too large for the amount of change 1 in the counting output, the white balance error can be minimized by increasing the number of counting bits, so the reversible counting circuit 16a, 16
The number of bits for the count b may be determined so as to fall within the white balance tolerance. Further, if the number of clock pulses generated by the pulse generation circuit 17 is set to 2N-1 or more, assuming that the number of counting bits of the reversible counting circuits 16a and 16b is N bits, all of the counting outputs of the reversible counting circuits 16a and 16b are set to 2N-1 or more. It can cover a wide range, and the clock pulse will not run out before the white balance is incorrect. A specific example of the pulse generating circuit 17 is shown in FIG. 4, and a waveform diagram is shown in FIG. However, the number of coefficient bits of the reversible counting circuits 16a and 16b is 3 bits. A dotted line 17 is a pulse generation circuit, which includes a NOR circuit 18, a T-type flip-flop with reset 19, 20,
21, 22, inversion circuit 23, vertical scanning synchronization signal input terminal 24, start pulse input 25, reversible counting circuit 16a
, 16b. Figure 5 A is the start pulse, the opening is the vertical scanning synchronization signal, C is the output of the inversion circuit 23, 2 is the output of the NOR circuit, T-shaped flip-flop 19 with reset
, 20, 21, 22 are shown. The operation will be explained. When the start pulse is input, all T-type flip-flops 19, 20, 21, and 22 are reset, and Q becomes 1 as shown in waveform diagrams 31 to 34. When the Q of the T-type flip-flop 22 becomes 1, an inverted signal of the vertical scanning synchronization signal is obtained as the output of the NOR circuit 18. When a T-type flip-flop is operated using this signal, signals of waveforms 31 to 34 are obtained. T-type flip flop 2
When the Q of 2 becomes 0, the output of the NOR circuit 18 becomes 01, and the operation of the T-type flip-flops 19 to 22 is stopped. It remains fixed until the next start pulse is applied. Therefore, when the signal obtained at the terminal 26 is used as a clock pulse for driving the 3-bit reversible counting circuits 16a and 16b, the number of pulses is obtained, covering the entire range of the 3-bit reversible counting circuits 16a and 16b. That's what I did. If the number of bits of the reversible counting circuits 16a and 16b is N, the same result as in the previous embodiment can be obtained by using N stages of T-type flip-flops with reset. Although this embodiment uses a vertical scanning synchronization signal, similar results can be obtained by using a signal asynchronous to the television synchronization signal.

As is clear from the above description, according to the present invention, the time required to adjust the white balance is constant.

By appropriately selecting the number of tick pulses, the white balance can be adjusted accurately and with a simple configuration without having to stop adjusting the white balance in the middle.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional flexor imaging device, FIG. 2 is a wiring diagram of the main parts, FIG. 3 is a block diagram of a flexor imaging device according to an embodiment of the present invention, and FIG. 4 is a pulse generation circuit. The connection diagram and FIG. 5 are signal waveform diagrams of the main parts thereof. 13a, 13b... Gain control circuit, 14a, 1
4b...DA converter, 15a, 15b...
... Increase/decrease discrimination circuit, 16a, 16b... Reversible counting circuit, 17. ．．・．． ．．・Pulse generation circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Scope of Claims] 1. A gain control circuit for controlling the gain of a color signal of a color imaging device, an increase/decrease discrimination circuit that generates a signal for discriminating increase/decrease in the gain, and the increase/decrease discrimination circuit driven by a clock pulse. A reversible counting circuit whose addition/subtraction is controlled by the output, a DA conversion circuit which DA converts the output of the reversible counting circuit, and a control signal generation means which generates a control signal for the gain control circuit using the output of the DA conversion circuit. and a clock pulse generator which is provided in each of at least two color transmission systems of the color imaging apparatus and generates a predetermined number of the clock pulses after starting. 2. As a clock pulse generator, a count circuit that uses a vertical scanning synchronization signal to count the number of pulses of the synchronization signal, and a gate circuit that gates the synchronization signal using the output of the count circuit. A color imaging device according to claim 1.