JPS6046457B2 - Memory check method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error checking method for a memory that employs the ECC method, and in particular, it checks information immediately before writing, stores the error address, and, in the event of a read error, checks the cause of the error. The present invention relates to a memory check method that refers to the stored contents of an error address in order to determine the error address.

2. Description of the Related Art As the degree of integration of semiconductor memory devices increases, the capacity of memory devices increases, and the demand for high reliability of memory devices increases.

For memory devices (memories for short) that employ the ECC method, various methods have been proposed that are capable of correcting 2-bit errors with so-called soft error countermeasures. However, these are measures against failures related to the memory array, address decoder, etc. that constitute the memory itself.
By the way, even with memory that uses the ECC method, if an error occurs in the information immediately before reading,
Reading the written information again usually does not cause problems as it can be corrected by the ECC mechanism.

However, in this case, the sending side of the write information or the ECC
If there is an error cause that occurs intermittently in the check bit generation function that is part of the mechanism, the true cause of the error may not be identified and may be overlooked as a soft error. Therefore, when such errors and true soft errors overlap, uncorrectable multi-bit errors that can lead to system failure occur frequently, which can lead to problems such as the need for extra maintenance time. . The purpose of the present invention is to
It is an object of the present invention to provide a method for easily knowing whether or not the cause of a read error is caused during writing when a read error is detected in a memory adopting the CC method.

According to the present invention, in a memory that employs the ECC method, a check circuit that checks written information when writing to the memory, an address memory that stores an error address detected by the check circuit during writing;
A memory check is provided with a function that refers to the address storage and compares it with the read address when a read error is detected during memory read, and makes it possible to identify whether the read error is caused by an error during writing. method is obtained.

The present invention will be described in detail below with reference to the drawings.

The figure is a block diagram showing one embodiment of the present invention. 1 is E
2 is an address decoder, 3 is a check bit generation circuit that generates redundant bits for error correction from data bits, and 4 is a memory that uses the CC method and stores data bits and check bits attached to them data·
A check circuit that checks written information from bits and check bits; 5 is an ECC circuit that checks read information from memory 1 and corrects it if there is a 1-bit error; and generates an alarm if there is an error of 2 or more bits; 6 is caused by the error signal detected when writing to memory 1.
Error in memory 1 ●Associative memory which is an address storage means, 7 is an address specification circuit of associative memory 6, 1
1 is a signal line through which data bits written to memory 1 are transferred, and 11a is a signal line for data bits read from memory 1.
12 is a signal line that transfers the memory address of memory 1, and 13 is a signal line that transfers the check bit generated by check bit generation circuit 3 to the outside through ECC circuit 5. signal line to be transferred to, 14
, 15 are signal lines for controlling read/write of the associative memory 7, respectively.

In the figure, when writing information to memory 1, check and
The bit generation circuit 3 generates 1 for the data bit.
A bit●check●bit for error correction is added, and the data●bit and check●bit are written to the memory address conveyed by the signal line 12.

Check circuit 4 is a check pin. This is a circuit that performs a parity check by combining data bits and check bits according to the same rules as when the data generating circuit 3 adds check bits to data bits to determine whether or not there is an error. . When the check circuit 4 detects an error, a write control signal is transmitted to the associative memory 6 via the signal line 14, and the associative memory 6 stores the memory address where the error was detected in writing to the memory 1.

Here, the associative memory 6 is a storage device that can be addressed according to the stored content, and as mentioned above, when an error is detected in the written information when writing to the memory 1, the error address This is address storage that stores sequentially. When the memory 1 is read and the ECC circuit 5 corrects a 1-bit error or detects a 2-bit error, the memory reference contents (read error detected) are sent to the addressing circuit 7 via signal lines 12 and 15. memory address) and a read control signal.

In the associative memory 6, when a match is detected by referring to the stored contents, the stored contents at the matching address are read out and sent to the outside. Although not shown in the figure, the parity created by the check circuit 4. Each bit output of the check circuit
Since the bit position is indicated, it is also possible to store the error bit position when storing the memory address in the associative memory 6, and the more you memorize it, the easier it will be to search for the cause of the failure. Become. If no match is detected in the associative memory 6, it can be assumed that there is no error when writing to the memory 1, and therefore it can be determined that there is some error occurrence factor in the memory 1 itself. Therefore, when an error is detected when reading the memory 1 river, it is determined whether the cause of the error is caused by memory 1 or another cause, and the identification result and memory address are stored by the maintenance program. This makes it possible to provide valuable clues for searching for system failures caused by memory devices or failures during maintenance.

As described above, according to the present invention, in a memory device that employs the ECC method, the information immediately before writing to the memory is checked and the error address is memorized. ,
Errors in the check bit generation circuit can now be detected,
This has the effect of facilitating maintenance of the memory device.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. In the figure, 1 is a memory, 2 is an address decoder, 3 is a check bit generation circuit, 4 is a check circuit, and 5 is an E
CC circuit, 6 is an associative memory which is an address storage means, 7
11, 11a, and 12 to 16 indicate an address designation circuit, and signal lines 11, 11a, and 12 to 16, respectively.

Claims (1)

[Claims] 1. In a memory that employs the ECC method, there is a check circuit that checks written information when writing to the memory, an associative memory means that stores the error address when an error is detected by the check circuit, and an associative memory means that stores the error address when reading the memory. A memory check method characterized by comprising means for referring to the associative memory means to determine whether a read address matches an error address at the time of writing when a read error is detected.