JPS6046643A - Method for collecting information on processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a processor information collection method, and in particular, to repair of a system control device in a distributed control exchange, separation from the system at the time of expansion, and influence of incorporation into the system. The present invention relates to a processor information collection method suitable for preventing such problems.

[Background of the invention]

An example of the configuration of a processor group in a conventional distributed control switch is shown in FIGS. 1 and 2. For example, referring to FIG. 1, this system includes an operation and maintenance processor group 1 and a plurality of network processor groups 2.
A, 6B. Here, the configurations of each processor group 1.2 and 3.4 are basically the same. For example, for processor group l, the operation and maintenance processors IOB and IIB have system control units 10A, 10A, and 10A, respectively. connected,
The system control devices 10A and IIA are connected to each other via a status communication signal line 5. And this system control device! The OA and IIA mutually send and receive information such as failure information and operating status information via the Q1 status communication signal line 5 that monitors failures in the operation and maintenance processors JOB and IIB.

In this way, a group of processors with a similar configuration 1゜2.3
．． 4, each of the system control devices 10A to 40A,
Buses 6A and 6B are connected to IIA to 41A,
system control device 10A in the continuous maintenance processor group 1;
The IIA collects information such as failure information and operating status information from the other processor groups 2 and 3.4 via the buses 6A and 6B.

The system shown in FIG. 2 is basically the same as the system configuration shown in FIG. 1, with the only difference being the way the buses 6A and 6B are connected.

However, in both the system configurations shown in FIG. 1 and FIG. 2, the system control devices 20A to 40A and 21A to 41A of the network processor group 2.3. In addition to requiring 7 bus circuits, it is necessary to disconnect buses 6A and 6B when repairing these system control devices, and to disconnect buses 6A and 6B when adding a new processor group.
The disadvantage is that the data on the buses 6A and 6B is easily affected when connecting to.

[Purpose of the invention]

An object of the present invention is to eliminate the drawbacks of the prior art described above, reduce the amount of hardware of the bus interface circuit of the system control device on the network processor side, and enable the operation and maintenance processor to collect information on all network processors. An object of the present invention is to provide a method for collecting processor information.

[Summary of the invention]

The present invention provides a redundant network processor that is provided for each redundant communication path network and performs switching control, a redundant operation and maintenance processor that performs operation and maintenance, and a redundant network processor that is provided for each processor system. In a distributed control exchange that has redundant system control devices, a bus that connects system control devices of the same system and transfers information, and a signal line that connects corresponding system control devices of different systems, the system on the operation and maintenance processor side Control device (first
The system control device on the network processor side (the second system control device) has a bus route designating means for specifying the bus route of either the own system or the other system, and the system control device on the network processor side (the second system control device) has a storage means for storing processor information. and the first
a selection means for selecting a unique second system control device based on unique information sent from the system control device; The processor information can be read and transferred to the first system control device via the bus designated by the bus route designation means. Thus, the first system control device can eventually collect information on all network processors via its own or other system bus or via a signal line.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a system configuration diagram of a distributed control exchange to which an embodiment of the present invention is applied. This system is configured by connecting a plurality of network processor groups 2, 3.4 to an operation and maintenance processor group 1 via buses 6A and 6B, and the configuration is as shown in FIGS. 1 and 2 above. It is similar to that.

In the operation and maintenance processor group I, the operation and maintenance processors IOB and IIB include a system control device 110A.

11A is connected, and the system control device 10A, II
A are connected to each other by a status communication signal line 5 and a detour bus 7. Therefore, this system control device 10A
, IIA is the own operation and maintenance processor IOB or I
Monitors the IB failure status, controls the regular and standby operation modes of the operation and maintenance processors IOB and IIB in both systems, and sends and receives processor information such as failure information and operating status information to and from each other via the status communication signal a5. are doing.

On the other hand, the plurality of network processor groups 2, 3 and 4 also have the same configuration as the operation and maintenance processor group 1. That is, each network processor group 2, 3.4 includes duplicated network processors 20B to 40B,
21B to 41B and these processors 20B to 40B
, a system control device 20 that monitors 21B to 41B.
A, 21A to 40A, and 41A.

In a system having such a configuration, the relationship between the regular system and standby system of each processor IO8-40B, IIB-41B of the operation/maintenance processor group 1 and the network processor groups 2, 3, and 4 is independent for each processor group.

System control devices 10A to 40A for each processor group.

11A to 41A are inter-system paths 6A and 6 for each system.
They are connected to each other at B. Therefore, the regular system control device in the operation and maintenance processor group l, for example, IOA,
Network processor groups 2, 3 .
It is possible to collect processor information such as fault information and operating status information of the processors of the entire network from the own system control devices 20A to 40A of No. 4. Furthermore, since it can also be connected to the system control devices 11A to 41A of other systems via the detour bus 7, processor information of all network processor groups, regardless of whether they are self or other systems, can be accessed from either the bus route 6A or 6B. can be collected.

Next, with reference to FIG. 4, the driving of the intersystem buses 6A and 6B of the system control devices 10A and IIA in the operation and maintenance processor group 1 will be described. In this example, it is assumed that the operation and maintenance processor JOB is the regular system, and the operation and maintenance processor IIB is the standby system. The configurations of the system control devices 10A and IIA are the same.

For example, in the system control device 10A, an instruction is given from the processor IOB as to whether to use the intersystem bus on the own side or on the other side. This instruction signal is input to the decoder 100, where it is decoded to determine which bus is to be used. Based on the decoding result, the bus route switching circuit 02 is activated. That is, when the own bus is specified, the bus route instruction signal a 103 is
) level and f! :,,c, When the other system bus is specified, this signal line 103 becomes low (L) level.

Here, a case where the own bus route is specified will be explained. In this case, if there is a bus startup command (designation of the route followed by processor 10B), this command is also decoded by the decoder 100 and the bus drive circuit 10
4 is activated. Then, a device number unique to each system control device is sent to the system control device designation signal path 105. A signal indicating this device number is transferred to the system control device on the network processor group 2.3.4 side via the tristate game (106) and transmission bus 300.

- 10,000, if a bus route of another system is designated by the decoding result of the bus route designation signal, the bus drive circuit 104 similarly selects the signal path 105, the tristate gate 106. A signal indicating the device number of the system control device is sent to the transmission bus 310 via the circular transmission bus 50A.

In the above case, the selection of the own system bus route or the other system bus route is determined by the OR product of the output signal of the gate 107, that is, the output signal of the normal system display signal line 101, the bus route instruction signal line 103, and the bus drive circuit 104. Determined by the case.

In this case, in the system control device 11A of the other system, since the regular system display signal line 101 is at @L# level, the gate 1
The output signal of 07 has “L” level and is tri-state.
Game) 106 is closed. Therefore, the transmission bus 300
, 310 have no effect.

By the operation explained above, network processor group 2
, 3.4 System control device power: When specified, gross information such as fault information and operating status information is returned from the specified system control device. Then, the bus drive circuit 104 spontaneously sends the device number of the next system ff1tl control device to the transmission node 300 or 310 without instructions from the broker 10B.

This bus drive operation continues to be executed as long as there is an instruction to stop bus drive from the processor IOB1.

Next, referring to FIG. 5, system release #device 10A.

The reception operation of processor information on the processor IOB and JIB sides in 11A will be explained. Incidentally, as in the explanation with reference to FIG. 4, system poison 1. Control device 10A
Suppose that it is a commonly used system.

Mass, bus route switching direction FM'r 102 Yo',j
ll % S#-) When a signal specifying the own system bus is output to the instruction signal line 103, network processor information is input from the reception bus 301 and stored in the reception buffer circuit 108 via the gate group of the system control device 10A. Ru.

At the same time, similar processor information is also transmitted to the backup system control device 11A via the detour receiving bus 50B and stored in the receiving buffer circuit 118 via the gate group. Note that the information stored in the receiving buffer 7 circuit 108 and 118 is read out according to instructions from the operation and maintenance processor IOB or IIB.

Now, when the processor information is stored in the reception buffer circuit 108, the reception buffer circuit 108 starts up the bus drive circuit 104 shown in FIG. 4, and the process moves to the next new bus drive sequence. In this state, bus route designation circuit 1
If 02 specifies a bus of another system, the reception buffer circuit 10
8, processor information is input from the reception bus 311 via the detour reception bus 51B and is stored therein. - Processor information is input directly to the reception buffer circuit 118 from the reception bus 311 and is stored therein. Note that at this time, the output of the backup path route switching circuit 112 is always at the "L" level on the bus route designation signal line 113.

Next, with reference to FIG. 6, the operation of the system control devices on the network processor side, such as 20A and 21A, will be described.

In this figure, one end of an intersystem bus 6A consisting of a transmission bus 300 and a reception bus 301 is connected to a system control device 10A on the operation and maintenance processor side.
The other end is connected to the system control devices 20A to 40A of each network processor group 2, 3.4. Similarly, the inter-system bus 6B consisting of the transmission bus 310 and the reception bus 311 is connected to each system control device 11A, 21.
Connected to A to 41A.

In such a configuration, for example, when the device number of a system control device on the transmission bus 300 is transferred, this device number is input to the own system device number comparison circuit 203 and the other system device number comparison circuit 204. .

On the other hand, from the system control device number setting circuit 200 to the system control device 20 through signal lines 201 and 202,
The device number of A is sent to comparison circuits 203 and 204.

If the comparison results in the comparison circuits 203 and 204 match, the output becomes "H" level.

That is, if the own system device numbers match in the comparison circuit 203, its output becomes "H" level, and the own system processor information in the own system processor information storage circuit 205 is transferred to the reception bus via the gate group and the trice gate 206. On the other hand, if the other system device numbers match in the comparison circuit 204, the other system processor information in the other system processor information storage circuit 215 is sent to the signal line 5.gate group and the trice ψ gate 206. The information is sent to the reception bus 301. The processor information sent to the reception bus 301 in this way is taken into the system control device of the operation and maintenance processor shown in FIG.

Note that in the system control device 21A, the transmission bus 31
0 to the comparison circuits 213 and 214 is compared with the device number from the system control device 28 number setting circuit 210, and is sent to the processor information storage circuit 215 in the same way as described above. or processor information in 205 is sent to receive bus 311 via gate group and trice gate 216.

In this way, the regular system operation and maintenance processor can read processor information from all network processors by the initial bus activation command. In particular, when disconnecting the system control device from the bus during system repair, or when installing it after repair or during expansion, repair work can be performed simply by switching the bus route.
This prevents any negative impact on the bus. Also, the bus interface of the system control device on the network processor side can be reduced to about half that of the conventional system.

〔Effect of the invention〕

As explained above, according to the present invention, the regular operation and maintenance gummy processor can easily collect processor information from all the network gummy processors. The amount of wear required is relatively small, and the economical effect is also great.

[Brief explanation of drawings]

1 and 2 are diagrams showing the configuration of a processor group and the bus configuration between system control devices according to the prior art, and FIG.
The figure shows the configuration of a processor group and the bus configuration between system control devices according to an embodiment of the present invention.
FIG. 3 is a diagram for explaining bus drive in the system control devices 10A and IIA shown in FIG. Figure 6 shows the third
It is a diagram showing an example of system control devices 20A and 21A shown in the figure. l...Operation and maintenance processor group, 2,3.4...Network processor group, IOA, IIA...Operation and maintenance processor side system control device, JOB, II
B...Operation and maintenance grossetsuza, 20A to 40A, 2
1A to 41A...Network processor side system control device, 20B to 4QB, 21B to 41B...
Network processor, 6A. 6B...Bus. Agent Patent Attorney Tadashi Akimoto Figure 1 Figure 2 Figure 3 Figure 4 Figure 0A Figure 6 11

Claims (1)

[Claims] A redundant network processor that performs exchange control, a redundant operation/maintenance processor that controls operation/maintenance, a redundant system control device provided for each processor system, and system control between the same systems. In a distributed control exchange that has a bus that connects devices and transfers information and a signal line that connects corresponding system control devices in different systems, the system control device on the operation/maintenance processor side is connected to either the own system or the other system. The system control device on the network processor side has a bus route designating means for specifying the bus route, and the system control device on the network processor side uses the storage means for accumulating processor information and the unique information sent from the system control device on the operation/maintenance side. It has a selection means for selecting a unique system control device, reads processor information from the storage means of the system control device selected by the selection means, and operates and maintains it via the bus designated by the bus route designation means. A processor information collection method characterized by transmitting information to a system control device on the processor side.