JPS6047068U - counting circuit - Google Patents

counting circuit

Info

Publication number
JPS6047068U
JPS6047068U JP13744583U JP13744583U JPS6047068U JP S6047068 U JPS6047068 U JP S6047068U JP 13744583 U JP13744583 U JP 13744583U JP 13744583 U JP13744583 U JP 13744583U JP S6047068 U JPS6047068 U JP S6047068U
Authority
JP
Japan
Prior art keywords
flip
outputs
instruction signal
counting circuit
flops
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13744583U
Other languages
Japanese (ja)
Inventor
篠田 一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13744583U priority Critical patent/JPS6047068U/en
Publication of JPS6047068U publication Critical patent/JPS6047068U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の計数回路が適用されるシステムの一例
を示すブロック図、第2図は本考案の一実施例を示す図
、第3図は第2図実施例の動作を示すタイムチャートで
ある。 2はカウント制御部、3は計数回路、FFはフリップフ
ロップ、CNT1〜3はカウンタ回路を示す。
Fig. 1 is a block diagram showing an example of a system to which the counting circuit of the present invention is applied, Fig. 2 is a diagram showing an embodiment of the invention, and Fig. 3 is a time chart showing the operation of the embodiment of Fig. 2. It is. 2 is a count control section, 3 is a counting circuit, FF is a flip-flop, and CNTs 1 to 3 are counter circuits.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ・ 計数開始を指示する指示信号及びクロック信号が入
力され、該指示信号が入力された時点より該クロック信
号の立上り或いは立下りを検出するフ、リップフロップ
と、該フリップフロップに直列に接続され、フリップフ
ロップの検出出力を計数するカウンタ回路とを備え、前
記フリップフロップの検出出力及び前記カウンタ回路の
出力を前記指示信号に対する計数値として出力する計数
回路。
- A flip-flop connected in series to the flip-flop, which receives an instruction signal for instructing the start of counting and a clock signal, and detects the rising or falling edge of the clock signal from the time the instruction signal is input; A counter circuit that counts detection outputs of flip-flops, and outputs the detection outputs of the flip-flops and the outputs of the counter circuit as a count value for the instruction signal.
JP13744583U 1983-09-05 1983-09-05 counting circuit Pending JPS6047068U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13744583U JPS6047068U (en) 1983-09-05 1983-09-05 counting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13744583U JPS6047068U (en) 1983-09-05 1983-09-05 counting circuit

Publications (1)

Publication Number Publication Date
JPS6047068U true JPS6047068U (en) 1985-04-02

Family

ID=30308717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13744583U Pending JPS6047068U (en) 1983-09-05 1983-09-05 counting circuit

Country Status (1)

Country Link
JP (1) JPS6047068U (en)

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