JPS6048593A - Signal display circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (a) Technical field of the invention The present invention relates to a signal display circuit for electronic equipment.

(b) Background of the technology For example, in a system consisting of a large number of electronic devices, such as an electronic meter, or a slave device having a large number of functions, it is necessary to display the status of the system or device to the operator. Or, if something goes wrong with the electronic device of the system or a specific function of the device, the problem occurs! ! h'? It is extremely important for the operation and security of electronic equipment to urgently display an alarm to the operator indicating that a cow has erupted. In recent years, with the digitization of electronic devices, many of these display signals are input digitally. For example, a signal of "1" when a signal is present, and "0" when a signal is not present is input as a display signal or It is called output.

This is sometimes referred to as "°1" indicating that the display signal is valid and "0" indicating that it is invalid.In any case, digitizing the display signal is a convenient method for display control and recording of display signals. It is.

However, in recent years, electronic devices have been expanded to process large amounts of information in a short amount of time, and if signals are not displayed efficiently, the display panel requires a large area and the display circuit becomes enormous. , becomes complicated. The present invention was devised from the viewpoint of simplifying and increasing the efficiency of this display circuit +tf
It's t+.

(C) Prior Art and Problems In the following, I will give two typical examples of signal display circuits that have been used in the past, and I will briefly discuss 271 points.

Figure 01 i+, Conventional display circuit vehicle 1 is system 1 of display circuit No. 111 that performs individual display using light emitting diodes? 1. Alarm 3 as a signal
“・Exhibit 13-Use example 9, ALM (1, 1, ・
・, 4 and 5 ammo display (rt-injury input is shown. In Fig. 1, l is a latch circuit and ALMo,
1. ..., 4 alarm display A, when the j input becomes ``1'', the latch circuit that received the 1 ``1'' status is about to be input again with ``0'' (normally). During this period, the latch circuit of driver circuit 2 is held at “1” until the
'' is maintained, a drive current is applied to cause the light emitting diode 3 in the next stage to emit light.This signal display circuit can display the number li'g at the same time if multiple signals are input at the same time. However, as the number of display signals increases, many circuit components are required, which occupies a large area of the display panel.

FIG. 2 is also one of the recent display circuits, and is a system diagram showing a signal display circuit in which one 7-segment light emitting diode operates in response to a plurality of signal inputs. A case is shown in which five alarm display signals are input as signals. Second
In the figure, 4 is an AND circuit (hereinafter referred to as A N l), 5 is a latch circuit, and 6-digit negation circuit (hereinafter referred to as N
7 is abbreviated as OR, 8 is a decoder/driver, and 9 is a 7-segment light emitting diode (hereinafter abbreviated as 7ST: G LED).

In FIG. 2, when all A and ■ inputs are normal and a signal of "0" is given to AND4, the latch circuit 5 becomes "0".
, the encoder 7 and decoder/driver 8 do not operate, and therefore the 78EG LED 9
i4 not displayed. ! On the other hand, since the input of NOR6 is "0°, 12 is outputted, and the input end of ANI)4 which is not a signal input is in the state of "1", forming a state in which it is waiting for signal input "1'.

Now, five inputs (one of the M numbers has fallen down, for example, AL/
When M2 inputs abnormal signal "1", AL
Both A of M2 and input of N D4 are ]"υ
, "1" is launched in the latch circuit 5 of AL82, and a predetermined code is formed in front of the 7-digit encoder 2, and the 8-digit decoder/driver 7ST82G LET) is displayed according to the code. On the other hand, since "1" is completed in the latch circuit 5 of ALrv+2, one of the inputs of N0R6 becomes 1", and the output of N0R6 becomes "0", which is input to the AND4 of Therefore, ALM2'°
After adding 1", AND4 does not accept any signal input. In this state, ALM2 continues at 1, which resets all the circuits every time. The signal display circuit in Fig. 2 emits light. Since there is only one diode, the number of parts is reduced slightly, but there is a drawback that multiple alarms cannot be displayed.

(d) Purpose of the Invention In view of the above-mentioned problems of the prior art, the present invention reduces the number of circuit components of a signal display circuit by t4' and 1. n It'
The display signal of i is generated and input at the same time, and -C is also input to the corresponding 47f.
1 = to enable sequential display of i-'3
(e) Structure of the Invention The present invention provides a method for inputting a plurality of display signals that cause the user to experience either valid or invalid information, and identifying the display signal input that corrects the valid information. In the display circuit that displays, the clock pulse of the furnace cycle is used to repeatedly output the binary number A3 with the number of digits corresponding to the total number of M numbers from the least significant digit to the first digit. a counting means, a screening means for searching the A-if display signal input according to the binary number and selecting the display signal to indicate the valid signal; Equation 1 has means for stopping the drive operation and displaying the binary signal at the time of stop with a 7-segment generator diode for identifying the duration, and the identification display is for single or plural identification by the counting means mentioned above. The display continues to be displayed repeatedly for each duration until the display signal becomes invalid, and if the duration is set to about 1 to 2 seconds, the display can be seen sufficiently, and the period of the clock pulse If the frequency is set to a short period of 1 microsecond at a time, the display f signal can be detected in an extremely short period of time even if the display signal ah'L increases. It is possible to make enough.

(f) Embodiment of the Invention Fig. 3 shows a system diagram of an embodiment of the signal display circuit according to the invention, and Fig. 4 shows a time chart of signals at various parts of the actual example.

In Fig. 3, the display number 13 that this signal display circuit handles as a failure takes an alarm signal as an example, and its i high number is ALM1, .
2. ..., 8 of 8. 10 is a clock pulse oscillator, 11V is an AND circuit (J
,;1. i' A N D), 12 is an octal count, 13 &:I is a multiplexer, 14 is a monostable multi-pibre (hereinafter abbreviated as monostable multi),
15iJ: decoder driver, 16 is a 7-segment emitting L diode (hereinafter abbreviated as 7SFJG LED)
, 17 of the inputs of multiplexer 13 represent enable inputs, and part A of the output of octal counter 12.

As shown by the waveform 21 of fi 41qJ, the oscillator 10 generates a pulse (i
T) Output a high clock pulse train. Now, let's show ourselves,
Alarm signal No. 1, No. t, is normal and "o '4H-;
When the input signal is input, the output of the multiplexer 13 (・go, all selected outputs play the display signal, monostable multi) 4's output (assumed to be "1", sif (therefore ANI)) 1iC is the corresponding one. The chronograph outputs the output and inputs it into the octal counter 12.

Octal counter 128-j: Binary counter 128-j: Binary counter 128-j: Since it handles eight display No. 43 inputs in the present embodiment, it is called an 8-a counter.

This 8-peak count 12 increments υ22 by 1 by U (clock pulse 2) shown in FIG. 4, and outputs signals A, B, and C as shown in waveforms 22, 23, and 24. AIB
The signals of and C are set to °0'' when No. 18 is absent, and are set to 1'' when it is present. One of these A, B, and C signals is input to the decoder driver 15, and the other is input to the multiplexer 13.

The decoder driver 13 outputs 7SEGLEDs 16 in accordance with the convention set in advance by the inputs of A, l (and C) mentioned above.
The number corresponding to the agreement will be displayed in a luminous manner.

For example, A, +3. C is I+, 0.0 (hereinafter A B
C ((100) and R11) as 1. ABC (010) 2. ABC (+1 (as if N is 3. However, Tecoder driver) i+ of 3: 'II work is monostable multi 1
With 40 inputs, fill 1, alarm 1, and no input, the output of the stable multi 14 is "]", which is 9 mouths in front, and the input 1 of this "1" is next to Otsu. sometimes degota driver 17
It is assumed that the 7SEG LED does not operate, and therefore the 7SEG LED does not emit light, indicating that no alarm signal is input and everything is normal.

Numbers 10C) to 402 are written at the bottom of Fig. 4, and these numbers indicate the shape f@ of each waveform in the curly brackets shown above, and indicate the shape of the circuit when the display signal is input. The four acids will be explained below according to the numbers.

When the display signal input is O', the above-mentioned states are states 100 to 105. Now, when the state is 106, A
If the display signal of L M 1 becomes 1'' and is input to the multiplexer 13, the ABC of the multiplexer 13
The input is 1 inch ABC (011) when in state 106.

In state 107, since ABC (111) is present, the multiplexer 13 cannot select the input of ALM1 yet, but
Status +: ABC (000) when 1OS and ALM
Choose l to be 1'IC, Jji stable multi 14
Output 0'
25.

When the output of the monostable multi 14 becomes 0'', the decoder/driver 15 (Gosaku ITJ) is activated and AI(C(+-1
00), so it is 7SI from the agreement σGL
■) Show the number 1 on 16 by lighting it up. 1- Power to indicate that APAMl has become abnormal,
In order to input the clock pulse to the output "O' of 8N D 11, the clock pulse stops at the top of the ISS, and the 811 counter] 2 stops the number movement and inputs ABC (000) to the output "O' of 8N D 11. Therefore, the 7SEG LED 16 continues to display the light emission of 2.
6 shows. The waveform 26 shows the emission status of the 7SgG LED 16, where 0 indicates no emission, 1 indicates l, 2. −．
8 Indicates that one of the numbers is illuminated.

The above-mentioned °C display situation where the number 1 of 73EG LEDl 6 occurs continues as long as the output of the monostable multi 14 changes from "0" to 1". This duration is determined by the circuit adjustment of the monostable multi 14. Although it can be arbitrarily determined, 1 to 2 seconds is sufficient if the operator only needs to be able to confirm the alarm display.Here, this is determined as ti1 second.

State 300 indicates a situation where the duration of 1 second is suitable. The output of the monostable multi 14 rises from "0" to "0" as shown in the waveform 25, and the decoder driver 15 outputs 7SEG.
Stop the light emission display of LEDl 6, ANDlli, j
Passing the clock pulse the octal counter is in state 300
ABC(000) from clock pulse moving from to 301
Start counting from the starting point.

Total iu, status 100, 101. -=, the process proceeds in the same order as 107, and when it reaches state 303, it returns to state 1.
The same situation as 08°109 was repeated and 7SEG Lg
At Dl 6, the number 1 indicating the status of ALMI is displayed.

As mentioned above, the display of the number 1 of 78EG LEDI 6 is performed intermittently for 1 second every 8 to 9 microseconds if the display signal input is AT, M].

In this situation (1liJ of a good human being), most of the generated electrons appear to be Gjy<ff-¥.

A L M 1 returns to normal υ input signal changes from "1" to 0'
When moving to 7SEG LF, if the D i 6 light emission is not displayed, the light emission will stop immediately, but if the light emission is on, the light emission will stop after the light emission duration of 1 second has elapsed. As shown in the state 400, the output of the quick stable multi 14 becomes 1', the 7SEG L1 D16if Zuiko stops, states 401 and 402, the octal counter 12 starts counting, and the multiplexer 13 returns to the initial state and displays the next display. Waits for signal input.

The above explanation is based on the case where there is one input of ]' of the display signal, but if there are multiple inputs, the above-mentioned states 300 to 30
3, the multiplexer 13 identifies a display signal input other than ALM1 and sends 7SEG LF to that input.
Display JD 16, octal count, 1
The outputs A, B and C of 2 repeat the multiple display signal input child identification display. Therefore, if all eight display signals are input, each -C ALM signal will be displayed by emitting light for 1 second at a time for 1 to 2 microseconds.

Even if there is a repeated display in this way, it is sufficiently visible to the operator for one second, and since each display is shown every 8 seconds, it does not particularly interfere with the detection and display of the display signal.

In this practical Neuha example, the total number of display signals is 8, but if the total number of display signals is 8 or more, the count output number of the counter and multiplexer and ijl+l! If you increase the number of different numbers, you can also add 7SEG
The number of LEDs may be increased to make a two-digit display, but if standard parts are used to reduce the cost of parts, the circuit configuration should be appropriate for the standard product.For example, by using a double circuit, When handling more than one display signal, use a multiplexer or multiple 8-f1A counters.

All you have to do is select a chip for the C multiplexer (g) 4. The present invention can reduce the number of circuit components for the signal display channel, and can be easily realized by using ready-made standard products. Even if multiple display signals occur simultaneously, they can be displayed sequentially.
It is highly expandable and allows you to easily increase the number of display signals even if the number of display signals to be handled increases.

[Brief explanation of drawings]

Figure 1 shows a system diagram of a 1-bar signal display circuit that performs individual display using light emitting diodes.
Sub/K E display circuit metal system 1 which has segment light emitting diodes in common F1〕□ and supplies multiple display signal inputs.
3. Ti,
Water circuit deficiency I) is shown in the system diagram
3 shows a time chart explaining the circuit function of the embodiment. In FIG. 3, ], Ol:l flock pulse oscillator,
11 is a logic row 1 circuit, 12 is an octal counter, 13 is a multi-frecou rt, 14 is a multi-frequency t+j: a Martino ζ ibrator, and 15 is a degouce-draino<, 16u
A seven-segment diode is shown, and b? 20 is the human input signal for alarm 1, 2 is the lock noggle, 22, 23 and 24 are the output signals of the if counter 12, 25 is the monostable multi-pie break output signal, and 26 is the 1.7 pigment output signal. 1゛1'; /I゛Indicates the firing status of the ion.f'i -1!X41・'
) Each A No. 1 δυ type 00 and 1 (・shows the status of τ signal “0” and “1”. Figure 1 Male 2 Figure 3

Claims (1)

[Claims] In a display circuit that inputs a plurality of display signals having either valid or invalid information and identifies and displays the display signal input having valid information, the display signal input is input from the lowest digit by a short-cycle clock pulse. A binary 2 counting means that repeatedly outputs a binary signal having a number of digits corresponding to the total number of digits in Ill['i next carry, and a binary 2 counting means that searches the display signal input using the binary signal and selects a display signal having the valid information. and a means for stopping the counting operation of the counting means for a predetermined duration according to the sorting and displaying a binary signal at the time of stopping by using a 7-segment light emitting diode to identify the duration; A signal display circuit characterized in that the above-mentioned counting means continues to display the identification display of a single tank or the number of tanks 11 times repeatedly for each of the durations until the display signal becomes invalid.