JPS6055111U - bias circuit - Google Patents

bias circuit

Info

Publication number
JPS6055111U
JPS6055111U JP14497783U JP14497783U JPS6055111U JP S6055111 U JPS6055111 U JP S6055111U JP 14497783 U JP14497783 U JP 14497783U JP 14497783 U JP14497783 U JP 14497783U JP S6055111 U JPS6055111 U JP S6055111U
Authority
JP
Japan
Prior art keywords
bias circuit
circuit
bias
gate
bias voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14497783U
Other languages
Japanese (ja)
Inventor
和正 岡村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14497783U priority Critical patent/JPS6055111U/en
Publication of JPS6055111U publication Critical patent/JPS6055111U/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図は、本考案によるバイアス回路を含む高周波増幅回路
の一実施例を示す図である。 １ａ・・・入力端子、１ｂ・・・出力端子、１ｃ・・・
電源端子、２・・・デュアルゲートＭＯ５−ＦＥＴ、３
・・・ツェナーダイオード、４・・・サーミスタ、５ａ
及び５ｂ・・・抵抗、６・・・チョークコイル、７・・
・高周波変成器、８ａ〜８ｃ・・・コンデンサ。The figure is a diagram showing an embodiment of a high frequency amplifier circuit including a bias circuit according to the present invention. 1a...input terminal, 1b...output terminal, 1c...
Power supply terminal, 2...Dual gate MO5-FET, 3
... Zener diode, 4... Thermistor, 5a
and 5b...resistor, 6...choke coil, 7...
・High frequency transformer, 8a-8c...capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第１のゲートに入力信号が印加され、第２のゲートにバ
イアス用電圧が印加されるＭＯＳ−ＦＥＴのバイアス回
路において、前記第２のケートニバイアス用電圧を印加
する回路に、抵抗及びサーミスタの並列回路を設けたこ
とを特徴とするバイアス回路。In a MOS-FET bias circuit in which an input signal is applied to a first gate and a bias voltage is applied to a second gate, a resistor and a thermistor are added to the circuit for applying the second Kethney bias voltage. A bias circuit characterized by having a parallel circuit.
JP14497783U 1983-09-21 1983-09-21 bias circuit Pending JPS6055111U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14497783U JPS6055111U (en) 1983-09-21 1983-09-21 bias circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14497783U JPS6055111U (en) 1983-09-21 1983-09-21 bias circuit

Publications (1)

Publication Number Publication Date
JPS6055111U true JPS6055111U (en) 1985-04-18

Family

ID=30323148

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14497783U Pending JPS6055111U (en) 1983-09-21 1983-09-21 bias circuit

Country Status (1)

Country Link
JP (1) JPS6055111U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137701A (en) * 1987-11-24 1989-05-30 Sumitomo Electric Ind Ltd Temperature compensating device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137701A (en) * 1987-11-24 1989-05-30 Sumitomo Electric Ind Ltd Temperature compensating device

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