JPS605532U - Processor operation monitoring circuit - Google Patents

Processor operation monitoring circuit

Info

Publication number
JPS605532U
JPS605532U JP9705183U JP9705183U JPS605532U JP S605532 U JPS605532 U JP S605532U JP 9705183 U JP9705183 U JP 9705183U JP 9705183 U JP9705183 U JP 9705183U JP S605532 U JPS605532 U JP S605532U
Authority
JP
Japan
Prior art keywords
monitoring circuit
operation monitoring
processor
processor operation
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9705183U
Other languages
Japanese (ja)
Inventor
一雅 井端
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Azbil Corp
Original Assignee
Azbil Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Azbil Corp filed Critical Azbil Corp
Priority to JP9705183U priority Critical patent/JPS605532U/en
Publication of JPS605532U publication Critical patent/JPS605532U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例のブロック図、第２図は本考案の実施例
を示すブロック図、第３図は他の実施例を示すブロック
図である。 ＣＰＵ・・・・・・プロセッサ、ＷＤＴ・・・・・・監
視タイマー、ＬＡＴ・・・・・・ランチ回路、ＣＵＴ−
、、−・・カウンタ、■Ｒ・・・・・・イニシャルリセ
ット信号。FIG. 1 is a block diagram of a conventional example, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing another embodiment. CPU...Processor, WDT...Monitoring timer, LAT...Launch circuit, CUT-
,, -... Counter, ■R... Initial reset signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プロセッサの動作を監視する監視タイマーと、電源の投
入に応じて生ずるイニシャルリセット信号によりリセッ
トされかつ前記監視タイマーの出力を保持すると共に保
持出力を前記プロセッサへ与える保持回路とを備えたこ
とを特徴とするプロセッサの動作監視回路。The present invention is characterized by comprising a monitoring timer that monitors the operation of the processor, and a holding circuit that is reset by an initial reset signal generated in response to power-on, holds the output of the monitoring timer, and provides a holding output to the processor. processor operation monitoring circuit.
JP9705183U 1983-06-23 1983-06-23 Processor operation monitoring circuit Pending JPS605532U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9705183U JPS605532U (en) 1983-06-23 1983-06-23 Processor operation monitoring circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9705183U JPS605532U (en) 1983-06-23 1983-06-23 Processor operation monitoring circuit

Publications (1)

Publication Number Publication Date
JPS605532U true JPS605532U (en) 1985-01-16

Family

ID=30231021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9705183U Pending JPS605532U (en) 1983-06-23 1983-06-23 Processor operation monitoring circuit

Country Status (1)

Country Link
JP (1) JPS605532U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57164320A (en) * 1981-04-02 1982-10-08 Nec Corp Reset system for microprocessor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57164320A (en) * 1981-04-02 1982-10-08 Nec Corp Reset system for microprocessor

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