JPS605741Y2 - Signal level conversion circuit - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a signal level conversion circuit used in liquid crystal display type digital electronic watches and the like.

In a liquid crystal display type digital electronic watch, the watch LSI that makes up the watch circuit can generally be sufficiently operated with a battery power supply voltage of about 1.5V, but at this voltage level, the liquid crystal display element cannot be driven. Therefore, it is necessary to convert it to a high voltage level of at least 3V.

Conventionally, as the above-mentioned signal level conversion circuit, the first
As shown in the figure, p-channel MO8 and n-channel MO
An R-S flip-flop system consisting of a complementary MO3 circuit 1.2 in which three MO3 circuits are combined has been proposed and put into practical use.

In the figure, Vss is a low voltage negative power supply (e.g. -1.5V)
, Vss2 is a high voltage negative power supply (for example -3v), VDD
indicates OV (earth).

The signal level conversion circuit of the above method is a complementary MO3 circuit 1.
, 2, the low voltage system signal IN is applied to the gate of p-channel MO3 of 2.
, IN are input, and level conversion is performed using the fact that the R-S flip-flop reaches a stable state in the high voltage system through its self-loop, and a signal with a voltage level necessary for driving the liquid crystal display element is extracted. ing.

That is, when the p-channel MOS transistor of the complementary MO3 circuit 2 is turned on, the voltage of VDD appears at the output OUT, and the n-channel MOS transistor of the complementary MO3 circuit 2 appears.
When the O3 transistor is turned on, the output OUT has V
The voltage of ss2 appears, thereby outputting a signal in which VDD is at the H1gh level, Vss2 is at the Low level, and the voltage level between them is about 3V.

However, in the above conventional level conversion circuit, the input signal changes from High to Low or from Low to High.
When the complementary pair of p-channel MO3,n
Since the channel MO3 both passes through the activated region, that is, the turn-on and turn-off times overlap with each other, and both the p-channel transistor and the n-channel transistor are conductive.
A through current flows to 8 and 2, resulting in an increase in current consumption.

Also, at the beginning of the above state inversion, p channel MO3 and n
Since the divided voltage due to the on-resistance of channel MO3 is applied to the gate of n-channel MO8 in the other complementary MO3 circuit, p-channel MO3 and n-channel MO3
This has the disadvantage that the on-resistance ratio of 0 varies, leading to a decrease in operating speed and instability.

This idea was made in order to eliminate the above-mentioned drawbacks of the conventional technology. It uses a pair of vertically connected complementary MOS inverters, and the operating voltage of the preceding complementary MOS inverter is controlled by the input signal level. Negative power supply■8,
To provide a signal level conversion circuit which eliminates an increase in current consumption due to through current and instability due to variations in process parameters by switching between .

An embodiment of this invention will be described below with reference to FIG.

In this FIG. 2, 10 is a p-channel MO310a.
and the complementary first − consisting of n-channel Mo8lOb
The f inverter 11 is a complementary second inverter consisting of the same<p channel O311a and n channel MO311b, and both inverters 1o and ii are connected between the output side (drain side) of the first inverter 10 and the second inverter 10. The input terminal IN of the first inverter 10 is connected vertically by directly connecting the input side (gate side) of the first inverter 10, and the voltage VDD is applied to the input terminal IN of the first inverter 10 at H1gh level ■8, 1 is set to Low
A low voltage system amplitude signal to be used as the level is input, and the output side (drain side) of the second inverter 11 is connected to the output terminal OUT, and the high voltage system operating voltage VDD Vss2 It is now being supplied.

Note that VDD represents OV (earth), Vss1 represents a low voltage negative power supply, and v8,2 represents a high voltage negative power supply.

12.13 is a bidirectional switch that alternately switches the operating power supply voltage of the first inverter 10 between Vss1 and Vss2, and these switches 12.13 are connected to a pair of p-channel MO3 and The dot-twin sides of the n-channel MO3s are directly connected to each other and connected to the source side of the n-channel MO3IQb of the first inverter 10, and each bidirectional switch 12.
A power supply voltage ~'3,1 or ■3,2 is applied to the source side of the switch 13, respectively, and furthermore, the n-channel MOS gate of the bidirectional switch 12 and the p-channel MO3 of the bidirectional switch 13 are applied. The output signal of the first inverter 10 is applied to the gate, and the output signal of the second inverter 11 is applied to the gate of the p-channel MO8 of the bidirectional switch 12 and the gate of the n-channel MO3 of the bidirectional switch 13. can be added to each.

Next, the operation of the signal level conversion circuit according to the invention constructed as described above will be explained.

An input signal a as shown in FIG. 3A is applied to the input terminal IN. First, the input signal a goes to a low level (
VS91. ) to I (high level (V=)).

In this case, the p-channel MO810a is turned off and the n-channel Mo81Ob is turned on, inverting the output of the first inverter 10 from High level to Low level.

Since the IJ)w level at this time is almost equal to the potential at point A in the circuit, the p-channel MO8 of the bidirectional switch 13
becomes semi-conductive, further lowering the potential at point A and simultaneously lowering the output level of the first inverter 10.

As a result, the p-channel MO3 of the second inverter 11
lia is ON, Snn channel Mo5lOb is OFF, and its output changes from Low level to High level (V
DD), and at the same time a stable state is reached in which switch 12 is turned on and switch 13 is turned off.

This means that the gate of p-channel MO3 of switch 12 is L.
ow level (■, 3□), the gate of the n-channel MO3 becomes High level (VDD), and the gate of the p-channel MO3 of switch 13 becomes High level (D'), the gate of the p-channel MO3 becomes High level (VDD). 1. ．． This is because it becomes the 0w level (VSS□).

Further, the potential at point A in this state becomes Vss2.

Next, in the above operating state, the input signal a to the circuit is H
When the level changes from high level to low level, the potential at point A is V9s2, so the p of the first inverter 10
Channel MO310a % n channel Mo5lO
b turns on and turns off, respectively, resulting in a semi-conducting state, and as a result, both MO310,
When a current momentarily flows from VDD to ■3 and 2 through 10b, the potential at point A rises to the VSS1 side, causing the MOS transistors in the turn-on and turn-off states to quickly shift to the on and off directions. Do it like this.

Therefore, the first inverter 10 senses the input signal as a low level and turns the n-channel Mo3lOb off.
F, n channel Mo8lOb is turned on and its output is inverted to High level (VDD).

As a result, the second inverter 11 is also inverted (p-channel MO3lla is turned off, n-channel MO311b is turned off).
N) [, sets the output to Low level and sets the output OUT to Low level (VSS2).

Additionally, along with this, the first and second inverters 10.1
The bidirectional switch 13 whose gate input is the output of
At N, the bidirectional switch 12 is in a stable state of being OFF.

At this time, the potential at point A becomes V B B 1.

Similarly, input signal a is set to LDW level and High level.
By changing to the h level, the first inverter 10
The output C of the second inverter 11 changes as shown in FIG. 3B, and the output C of the second inverter 11 changes as shown in FIG. 3C.

Further, the potential at point A is as shown in the third diagram.

Therefore, V3B□=-1,5V, VSE+2"-3v
and V oo ”Qv, and if an input signal with the waveform and voltage level shown in FIG. In other words, it is possible to take out a voltage signal with a voltage level difference of 3V by setting C1 in FIG. 3, that is, VDD to a high level and Vss2 to a low level.

Then, the first inverter 10 is activated by the switch 12.13.
V s s 2 g V s s 1 according to the inversion of the input signal to High and LOW levels,
Since this method is used to quickly switch to a stable state, current consumption due to through current is reduced, and level conversion can be stabilized.

As described above, in the signal level conversion circuit of this invention, the operating voltage of the first inverter is switched between the low voltage system side and the high voltage system side by means of two switches whose control inputs are the outputs of the 11th and 2nd inverters. This eliminates short-circuiting caused by the MOS being completely turned on in a transient state where the input signal level is reversed, thereby reducing the inverter's through current, and quickly stabilizing the switching operation of the second inverter. Since it is possible to make a transition from one state to another, stable and high-speed operation is possible even if there are variations in process parameters.

[Brief explanation of the drawing]

Fig. 1 is a wiring diagram showing a conventional signal level conversion circuit, Fig. 2 is a wiring diagram showing an example of the signal level conversion circuit according to this invention, and Fig. 3 is a time chart showing the operation of the circuit shown in Fig. 2. . 10...First inverter, 10a...
・p channel MO3, 1Ql)...n channel MO3, 11...second inverter, 11
a...p channel MO3, 11b""n channel/L/MO3, 12. 13...Bidirectional switch.

Claims (1)

[Scope of utility model registration request] a first inverter made of a complementary type MO3 that receives a low voltage system signal as an input; a second inverter made of a complementary type MO3 that uses the output of this first inverter as an input and uses a high voltage system as an operating power source; A signal level consisting of a pair of bidirectional switches connected to switch the operating voltage of the first inverter between a low current system and a high voltage system, and having the outputs of the first and second inverters as control inputs. conversion circuit.