JPS6059632U

JPS6059632U - phase comparator

Info

Publication number: JPS6059632U
Application number: JP14964683U
Authority: JP
Inventors: 藤岡　文夫
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1983-09-29
Filing date: 1983-09-29
Publication date: 1985-04-25

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の位相比較器を用いたＰＬＬ回路のブロッ
ク図、第２図は第１図の位相比較器の動作を示すタイミ
ング図、第３図は従来の他の位相比較器を用いたＰＬＬ
回路のブロック図、第４図は第３図の位相比較器の動作
を示すタイミング図、第５図は本考案の一実施例の位相
比較器を用いたＰＬＬ回路のブロック図、第６図、第７
図は第５図の位相比較器の動作を示すタイミング図、第
８図は第５図の位相比較器の位相比較特性図である。１０・・・位相比較器、１１・・・データ入力端子、１
２・・・クロック入力端子、１３・・・アンドゲート、
１４Ａ、１４Ｂ・・・微分回路、１５・・・Ｒ−３−Ｆ
Ｆ。１６Ａ、１６Ｂ・・・積分回路、１７・・・減算回路、
１８・・・位相比較出力端子、２０・・・ループフィル
タ、３０・・・ｖＣＯ１３１・・・再生クロック出力端
子。Figure 1 is a block diagram of a PLL circuit using a conventional phase comparator, Figure 2 is a timing diagram showing the operation of the phase comparator in Figure 1, and Figure 3 is a PLL circuit using another conventional phase comparator. PLL
A block diagram of the circuit, FIG. 4 is a timing diagram showing the operation of the phase comparator of FIG. 3, FIG. 5 is a block diagram of a PLL circuit using the phase comparator of an embodiment of the present invention, and FIG. 7th
5 is a timing diagram showing the operation of the phase comparator of FIG. 5, and FIG. 8 is a phase comparison characteristic diagram of the phase comparator of FIG. 5. 10... Phase comparator, 11... Data input terminal, 1
2... Clock input terminal, 13... AND gate,
14A, 14B... Differential circuit, 15... R-3-F
F. 16A, 16B... Integration circuit, 17... Subtraction circuit,
18... Phase comparison output terminal, 20... Loop filter, 30... vCO131... Regenerated clock output terminal.

Claims

[Scope of utility model registration request]

(1) A flip-flop that is set at the rising edge (falling edge) of data and reset at the falling edge (rising edge) of a clock serving as a reference for comparison, and an AND circuit that performs an AND operation between the data and the clock; A phase comparator comprising a difference signal generating means for generating a signal representing the difference between the pulse width of the output pulse of the flip-flop and the six pulse width of the output pulse of the AND circuit.

(2) The difference signal generating means includes a first integrator circuit connected to the rear stage of the flip-flop, a second integrator circuit connected to the rear stage of the AND circuit, the second integrator circuit and the first integrator circuit. 2. A phase comparator according to claim 1, which is characterized by comprising: an integrating circuit; and a subtracting circuit which performs subtraction upon receiving the respective outputs.