JPS6059879A - Video amplifier circuit - Google Patents

Video amplifier circuit

Info

Publication number
JPS6059879A
JPS6059879A JP58168766A JP16876683A JPS6059879A JP S6059879 A JPS6059879 A JP S6059879A JP 58168766 A JP58168766 A JP 58168766A JP 16876683 A JP16876683 A JP 16876683A JP S6059879 A JPS6059879 A JP S6059879A
Authority
JP
Japan
Prior art keywords
circuit
potential
bases
transistor
differential amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58168766A
Other languages
Japanese (ja)
Other versions
JPS6352515B2 (en
Inventor
Ikuo Kadota
門田 郁雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP58168766A priority Critical patent/JPS6059879A/en
Publication of JPS6059879A publication Critical patent/JPS6059879A/en
Publication of JPS6352515B2 publication Critical patent/JPS6352515B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/57—Control of contrast or brightness

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)
  • Television Receiver Circuits (AREA)

Abstract

PURPOSE:To prevent a screen from being made black by connecting a resistor between bases of both transistors (TRs) of a differential amplifier and setting the bases to almost the same potential in terms of DC in a video amplifier circuit of a color television receiver. CONSTITUTION:In setting a channel to an idle channel, no burst gate pulse appears at a terminal 13 and a base potential of a TR5 tends to fall down. Since a resistor 23, however, is connected between both bases of TRs 4, 5, the bases are brought into almost the same potential and the collector potential of the TR5 does not reach a voltage VCC applied to a DC power supply terminal 15. Thus, the differential amplifier 3 acts like differential operation and a potential appears at the base of the TR4 accordingly in response to a signal appearing via a contrast adjusting circuit 1.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明はテレビ受像機の映像増幅回路に係り、特に空き
チャンネルに設定したときのテレビ画面の不都合を除去
した新規な構成による映像増幅回路に関する。
Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a video amplification circuit for a television receiver, and in particular to a video amplification circuit with a novel configuration that eliminates the inconvenience of the television screen when it is set to an empty channel. Regarding.

(ロ)従来技術 一般にカラーテレビ受像機の映像増幅回路は、第1図に
示すようにコントラスト調整回路(1)の出力端にエミ
ッタフォロアトランジスタ(2)、差動増幅器(yを構
成する一対のトランジスタ(41(5)、直流再生及び
輝度調整回路(句が順次接続され、前記コントラスト調
整回路(、Llにはコントラスト調整用の可変抵抗器(
力が、一方直流再生及び輝度調整回路(句には輝度調整
用の可変抵抗器(8)が各々接続されている。
(b) Prior Art Generally, as shown in Figure 1, the video amplification circuit of a color television receiver has an emitter follower transistor (2) at the output end of a contrast adjustment circuit (1), and a pair of differential amplifiers (y). A transistor (41 (5), a DC regeneration and brightness adjustment circuit (2) are connected in sequence, and a contrast adjustment circuit (Ll) is connected to a variable resistor (Ll) for contrast adjustment.
On the other hand, a DC regeneration and brightness adjustment circuit (a variable resistor (8) for brightness adjustment is connected to each side).

端子(9)は複合映像信号が印加される入力端子、00
)は結合コンデンサ、01)は定電流回路、02はペデ
スタルレベルホールド用のコンデンサ、 (13)ハハ
ーストゲートパルス印加端子、(14)は映像出力端子
、(19は直流電源端子、(16)はアース端子、0η
(+81はエミッタ7オロアトランジスタを示す。
Terminal (9) is an input terminal to which a composite video signal is applied, 00
) is a coupling capacitor, 01) is a constant current circuit, 02 is a capacitor for pedestal level hold, (13) Hahurst gate pulse application terminal, (14) is a video output terminal, (19 is a DC power supply terminal, (16) is Earth terminal, 0η
(+81 indicates the emitter 7 oror transistor.

次に第1図の動作について説明すると、上記入力端子(
9)に複合映像信号が印加された場合、該映像信号のバ
ックポーチ期間に挿入されたカラーバースト信号を取出
すためのパーストゲートパルス(以下BGPと称する)
によって直流再生及び輝度調整回路(句をゲートし、映
像信号のベデスタルレベルを輝度調整用の可変抵抗器(
8)で調整された所定の電圧に一致させる。走査期間は
前記コンデンサa2)の働きによってパルス期間と同一
のペデスタルレベルが保持される。このとき空きチャン
ネル時、前記BGPが端子α3)に印加されないことか
ら、トランジスタ(5)のベース電位が下がってアース
電位に近くなってしまい、該トランジスタ(5)のコレ
クタ電位は、電源電圧vccまで上昇するので、差動増
幅器(yは差動増幅として動作せず、又エミッタフォロ
接続したトランジスタ(17)のエミッタ電流が増大し
て次段のトランジスタ(18のベース電位も上昇し、こ
れに伴って端子a4の電位が上昇するので、ペデスタル
レベルが高くなって、テレビ受像機の画面は真っ黒に近
づく。
Next, to explain the operation shown in Figure 1, the above input terminal (
When a composite video signal is applied to 9), a burst gate pulse (hereinafter referred to as BGP) for extracting a color burst signal inserted in the back porch period of the video signal.
Gating the DC reproduction and brightness adjustment circuit (phrase), the vedestal level of the video signal is connected to the variable resistor (for brightness adjustment).
8) to match the predetermined voltage adjusted in step 8). During the scanning period, the same pedestal level as during the pulse period is maintained by the function of the capacitor a2). At this time, when the channel is empty, the BGP is not applied to the terminal α3), so the base potential of the transistor (5) drops and becomes close to the ground potential, and the collector potential of the transistor (5) reaches the power supply voltage vcc. As a result, the differential amplifier (y) does not operate as a differential amplifier, and the emitter current of the emitter follow-connected transistor (17) increases, and the base potential of the next stage transistor (18) also rises. Since the potential at terminal a4 increases, the pedestal level becomes high and the screen of the television receiver approaches pitch black.

従ってそれ迄の輝度調整用の可変抵抗器(8)の設定位
置から変化させても画面は明る(ならず、使用者はテレ
ビ受像機が故障したのではないかと勘違いしてしまう欠
点があった。
Therefore, even if you change the setting position of the variable resistor (8) for brightness adjustment, the screen will not be bright (there is a drawback that the user may think that the TV receiver is malfunctioning). .

そこで上記欠点を除去するために、第1図の破線で示し
た集積回路(IC)の外部に水平の帰線消去パルス(ブ
ランキングパルス)を用いて、前記BGPの代りのパル
スを生成し、前記直流再生及び輝度調整回路16)に加
えていたが、この方法は回路構成が複雑になると共KI
C化したメリットが活かし切れない欠点が生じる。
Therefore, in order to eliminate the above drawback, a horizontal blanking pulse (blanking pulse) is used outside the integrated circuit (IC) shown by the broken line in FIG. 1 to generate a pulse in place of the BGP, The DC regeneration and brightness adjustment circuit 16) was added to the DC regeneration and brightness adjustment circuit 16), but this method requires complicated circuit configuration and KI
There is a drawback that the advantages of C conversion cannot be fully utilized.

(ハ)発明の目的 本発明は、従来空きチャンネル時パーストゲ−゛−トパ
ルスがないことに起因して直流再生及び輝度調整回路の
不動作に伴い画面が真っ黒になるのを防止し、所定の明
るさの画面を保つことを目的とする。
(c) Purpose of the Invention The present invention prevents the screen from becoming completely black due to the non-operation of the DC regeneration and brightness adjustment circuits due to the lack of burst gate pulses when the channel is empty, and maintains a predetermined brightness level. The purpose is to keep the screen as clear as possible.

(ロ)発明の構成 本発明は、順次接続されたコントラスト調整回路、直流
再生回路及び輝度調整回路を有し、該コントラスト調整
回路の出力端と直流再生回路の入力端に接続した差動増
幅器と、該差動増幅器の一方のトランジスタのペースと
アース間に接続されたペデスタルレベルホールド用コン
デンサとヲ備え、前記差動増幅器を構成する両トランジ
スタのベース間に抵抗を接続して、前記ベースを直流的
に略同電位に設定するものである。
(b) Structure of the Invention The present invention has a contrast adjustment circuit, a DC regeneration circuit, and a brightness adjustment circuit connected in sequence, and a differential amplifier connected to the output end of the contrast adjustment circuit and the input end of the DC regeneration circuit. , a pedestal level hold capacitor connected between the base of one of the transistors of the differential amplifier and ground, and a resistor connected between the bases of both transistors constituting the differential amplifier to connect the base to the DC current. They are set to approximately the same potential.

(ホ)実施例 図面に従って本発明を説明すると、第2図は本発明の映
像増幅回路を示し、第1図と同一素子については同一図
番を付してあり、轡は直流再生回路、■は輝度調整回路
、c2H壜まエミッタ抵抗、e渇は差動増幅器■)の各
トランジスタ(4)(5)の両ベースに接続した抵抗、
e(イ)は基準電圧印加端子を示す。
(E) Example The present invention will be explained according to the drawings. Fig. 2 shows a video amplification circuit of the invention, and the same elements as in Fig. 1 are given the same figure numbers. is the brightness adjustment circuit, c2H is the emitter resistor, and e is the resistor connected to both bases of each transistor (4) and (5) of the differential amplifier.
e (a) indicates a reference voltage application terminal.

次に第2図の動作について説明すると、入力端子(9)
に複合映像信号を加えて、コントラスト調整回路(1)
に接続された可変抵抗器(7)にて所望のコントラスト
に設定する。該コントラスト調整回路(1)の出力端は
エミッタフォロアトランジスタ(2)を介して差動増幅
器■が接続されており、通常の受信時は端子Q31にB
GPが印加されるので、これに同期して直流再生回路U
はゲートされ、映像信号のペデスタルレベルを基準電圧
に一致させる。この基準電圧は、輝度調整回路(錘がオ
フ時、ペデスタルレベルを最黒レベルになる様に設定し
ておく。
Next, to explain the operation in Figure 2, the input terminal (9)
Adding a composite video signal to the contrast adjustment circuit (1)
The desired contrast is set using a variable resistor (7) connected to the . The output terminal of the contrast adjustment circuit (1) is connected to a differential amplifier ■ via an emitter follower transistor (2), and during normal reception, B is connected to terminal Q31.
Since GP is applied, in synchronization with this, the DC regeneration circuit U
is gated to match the pedestal level of the video signal to the reference voltage. This reference voltage is set so that the pedestal level becomes the blackest level when the brightness adjustment circuit (weight) is off.

次に輝度調整回路(社)において、輝度調整用の可変抵
抗器(8)で調整された電圧にペデスタルレベルを一致
させ−0最適な明るさの画面が得られる。
Next, in the brightness adjustment circuit (Inc.), the pedestal level is made to match the voltage adjusted by the variable resistor (8) for brightness adjustment, so that a screen with optimum brightness is obtained.

出力端子α4からは所定の映像信号(Yout)が得ら
れ、該端子α荀に映像出力トランジスタ(図示せず)を
接続すれば、該映像出力トランジスタから映像出力が取
出される。
A predetermined video signal (Yout) is obtained from the output terminal α4, and if a video output transistor (not shown) is connected to the terminal α4, the video output is taken out from the video output transistor.

今チャンネルを空きチャンネルに設定した場合、端子り
にBGPが現われず、コンデンサ(121の接続された
端子(2ツ即ちトランジスタ(5)のベース電位は下ろ
うとする。
If the channel is now set as an empty channel, BGP will not appear on the terminal, and the base potential of the two terminals connected to the capacitor (121, that is, the transistor (5)) will try to fall.

ところが前記トランジスタ(4)(5)の両ベース間に
抵抗(23)を接続しであるので、そのベースは略同電
位となって、従来の様にトランジスタ(5)のコレクタ
電位が直流電源端子(15+に加えられる電圧Vccに
達することはなく、従って差動増幅器(3)は差動の動
作を行い、これに伴ってトランジスタ(4)はコントラ
スト調整回路(1)を介して現われる信号に応じてその
ペースには電位が現われる。
However, since the resistor (23) is connected between the bases of the transistors (4) and (5), the bases are at approximately the same potential, and the collector potential of the transistor (5) is equal to the DC power supply terminal as in the conventional case. (The voltage Vcc applied to 15+ is never reached, so the differential amplifier (3) performs a differential operation, and accordingly the transistor (4) responds to the signal appearing via the contrast adjustment circuit (1). A potential appears at that pace.

ここでBGPが端子α陣に現われる場合、前記基準電圧
(Vref)にペデスタルレベルが一致したときのトラ
ンジスタ(5)のコレクタ電圧をV。とすると、このと
き抵抗(21)(23の値R1とR2の比を所定の値に
選べば、トランジスタ(5)のコレクタ電位を■。に設
定することができる。
Here, when BGP appears on the terminal α group, the collector voltage of the transistor (5) when the pedestal level matches the reference voltage (Vref) is V. In this case, if the ratio of the values R1 and R2 of the resistors (21) (23) is selected to a predetermined value, the collector potential of the transistor (5) can be set to .

(へ)発明の効果 本発明の映1象増幅回路によれば、従来のように空きチ
ャンネル設定時において、BGPが現われないことに起
因する差動増幅器の一方のトランジスタのベース電位の
降下に伴ってテレヒ受像機の画面が真っ黒になるのを未
然に防止し得、又実施例における可変抵抗器及びペデス
タルレベル保持用のコンデンザ以外IC化した場合、外
部素子として何ら設ける必要はないので、本発明はカラ
ーテレビ受像機における映像増幅回路のIC化にも大い
に寄与すること犬である。
(F) Effects of the Invention According to the one-parameter amplifier circuit of the present invention, when an empty channel is set as in the conventional case, the base potential of one transistor of the differential amplifier decreases due to the fact that BGP does not appear. This invention can prevent the screen of a TV receiver from becoming completely black, and if the variable resistor and the capacitor for maintaining the pedestal level in the embodiment are implemented as an IC, there is no need to provide any external elements. It also greatly contributed to the use of ICs for video amplification circuits in color television receivers.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の映像増幅回路、第2図は本発明の同回路
を示す。 主な図番の説明
FIG. 1 shows a conventional video amplification circuit, and FIG. 2 shows the same circuit according to the present invention. Explanation of main drawing numbers

Claims (1)

【特許請求の範囲】[Claims] (1) 順次接続されたコントラスト調整回路、直流再
生回路及び輝度調整回路を有し、該コントラスト調整回
路の出力端と直流再生回路の入力端に接続した差動増幅
器と、該差動増幅器の一方のトランジスタのペースとア
ース間に接続されたペデスタルレベルホールド用コンデ
ンサとヲ備工、前記差動増幅器を構成する両トランジス
タのペース間に抵抗を接続して、前記ペースを直流的に
略同電位に設定することを特徴とした映像増幅回路。
(1) A differential amplifier having a contrast adjustment circuit, a DC reproduction circuit, and a brightness adjustment circuit connected in sequence, and connected to the output terminal of the contrast adjustment circuit and the input terminal of the DC reproduction circuit, and one of the differential amplifiers. A pedestal level hold capacitor and a capacitor are connected between the transistor pace and the ground, and a resistor is connected between the transistor paces of both transistors constituting the differential amplifier, so that the paces are at approximately the same potential in terms of direct current. A video amplification circuit characterized by configurable settings.
JP58168766A 1983-09-12 1983-09-12 Video amplifier circuit Granted JPS6059879A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58168766A JPS6059879A (en) 1983-09-12 1983-09-12 Video amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58168766A JPS6059879A (en) 1983-09-12 1983-09-12 Video amplifier circuit

Publications (2)

Publication Number Publication Date
JPS6059879A true JPS6059879A (en) 1985-04-06
JPS6352515B2 JPS6352515B2 (en) 1988-10-19

Family

ID=15874049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58168766A Granted JPS6059879A (en) 1983-09-12 1983-09-12 Video amplifier circuit

Country Status (1)

Country Link
JP (1) JPS6059879A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162487A (en) * 1987-12-18 1989-06-26 Sanyo Electric Co Ltd Video amplifying circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162487A (en) * 1987-12-18 1989-06-26 Sanyo Electric Co Ltd Video amplifying circuit

Also Published As

Publication number Publication date
JPS6352515B2 (en) 1988-10-19

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