JPS60642U - input/output control device - Google Patents
input/output control deviceInfo
- Publication number
- JPS60642U JPS60642U JP9268183U JP9268183U JPS60642U JP S60642 U JPS60642 U JP S60642U JP 9268183 U JP9268183 U JP 9268183U JP 9268183 U JP9268183 U JP 9268183U JP S60642 U JPS60642 U JP S60642U
- Authority
- JP
- Japan
- Prior art keywords
- address
- input
- output
- control device
- counter circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bus Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案のもとになる従来技術を説明するための
データ処理装置の構成図、第２図は本考案の一実施例を
示すブロック構成図、第３図は第２図の実施例を説明す
るための図である。
１０１・・・・・・中央処理装置、１０２・・・・・・
主記憶装置、１０３〜１０４・・・・・・入出力制御装
置、１０５゜２００・・・・・・入出力バス、１０６，
２１０・・・・・・入出力装置、１１０・・・・・・ア
ドレスカウンタ回路、１１１．２０３・・・・・・レン
ジカウンタ回路、１１２゜２０４・・・・・・制御回路
、１１３・・・・・・緩衝記憶回路、２０１・・・・・
・第１のアドレスカウンタ回路、２０２・・・・・・第
２のアドレスカウンタ回路、２０５・・・・・・アドレ
ス切替回路、２０６・・・・・・データレジスタ。Fig. 1 is a block diagram of a data processing device for explaining the conventional technology on which the present invention is based, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is an implementation of Fig. 2. FIG. 3 is a diagram for explaining an example. 101...Central processing unit, 102...
Main storage device, 103-104... Input/output control device, 105°200... Input/output bus, 106,
210...Input/output device, 110...Address counter circuit, 111.203...Range counter circuit, 112°204...Control circuit, 113... ...Buffer memory circuit, 201...
- First address counter circuit, 202... Second address counter circuit, 205... Address switching circuit, 206... Data register.
Claims (1)
モリアクセスを行う入出力制御装置において、前記主記
憶装置との転送アドレスを指定する第１のアドレスカウ
ンタ回路と、同じく第２のアドレスカウンタ回路と、前
記主記憶装置との転送レンジを指定し前記第１、第２の
アドレスカウンタ回路に連動するレンジカウンタ回路と
、該レンジカウンタ回路の制御出力により前記第１のア
ドレスカウンタ回路の出力と第２のアドレス功つンタの
出力とを切替えて主記憶装置に出力するアドレス切替回
路と、更に前記主記憶装置と該入出力制御装置間におけ
るデータ転送を制御する制御回路とから構成され、前記
主記憶袋−に対し高速かつ連続的なデータ転送を行うこ
とを特徴とじた入出力制御装置。In an input/output control device that performs direct memory access to a main memory in an electronic computer system, the main memory includes a first address counter circuit that specifies a transfer address to the main memory, a second address counter circuit, and the main memory. a range counter circuit that specifies a transfer range with the device and interlocks with the first and second address counter circuits, and a control output of the range counter circuit that allows the output of the first address counter circuit to match the second address. an address switching circuit that switches the output of the printer and outputs it to the main storage device, and a control circuit that controls data transfer between the main storage device and the input/output control device. An input/output control device characterized by high-speed and continuous data transfer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9268183U JPS60642U (en) | 1983-06-15 | 1983-06-15 | input/output control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9268183U JPS60642U (en) | 1983-06-15 | 1983-06-15 | input/output control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60642U true JPS60642U (en) | 1985-01-07 |
Family
ID=30223009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9268183U Pending JPS60642U (en) | 1983-06-15 | 1983-06-15 | input/output control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60642U (en) |
-
1983
- 1983-06-15 JP JP9268183U patent/JPS60642U/en active Pending
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