JPS6068442A - Data processor - Google Patents

Abstract

PURPOSE:To improve the performance of a CPU by converting the instruction and data logical addresses of approximately equal capacity into real addresses, and applying the result of this converstion to a prescribed circuit. CONSTITUTION:The instruction and data logical addresses are sent to instruction and data logical registers 4011 and 4012 to be applied with data address conversions are supplied to instruction and data real address registers 5011 and 5012, respectively. Then the output of the register 5011 is set to an instruction buffer 5021, and the output of the buffer 5021 is supplied to an arithmetic controller via an instruction local register 5031. While the output of the register 5012 is sent to a data buffer 5022, and the output of the buffer 5022 is supplied to an instruction decoding operand address device via a data buffer 5032.

Description

[Detailed description of the invention] The present invention relates to a data processing device.

The Daisei Central Processing Unit, which achieves high processing power, is equipped with an address conversion unit that converts logical addresses into addresses in the main memory, and a nokura unit that stores some information in the main memory. However, as the control of central processing units has become increasingly automated, read requests for instructions and operand data have caused competition between the address translation unit and the processor unit, making it difficult to improve the performance of medium-temperature processing units. has become an obstacle.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that has a mishit rate equivalent to that of the prior art and can improve the performance of a central processing unit.

The device of the present invention includes a storage means for storing all commands and data, a plurality of gun ejection means for extracting the entire contents of the storage means, and an instruction storage means for storing a copy of a part of the optical command stored in the storage means. means; and data storage means having a storage capacity the same as or substantially the same as the storage capacity of the instruction storage means and storing a copy of a portion of the data stored in the storage means.

instruction address converting means, when a logical address of an instruction is given from one of the plurality of reading means, converts the logical address into a real address of the storage means and provides the conversion result to the instruction storage means; and data address converting means for converting the logical address into a real address of the storage means when a logical address of data is given from one of the plurality of reading means and providing the conversion result to the data storage means. It is characterized by

FIG. 1 is a diagram showing an example of a conventional data processing device. The instruction read control unit 1 sends the storage address of the instruction on the main memory in the form of a logical address (hereinafter referred to as an instruction logical address) to the address conversion unit 4 via the signal wirework 4. The unit 4 stores the instruction logical address in the main memory unit 6.
After converting the upper actual address (J lower lower address K), transfer this address to buffer unit 5 and signal line 4.
Not sent via 5. If the information necessary for 5 address conversion does not exist in the unit 4, a request is made to read out the necessary information from the unit 6 via the signal line 46, and in response to the request, the information is read out via the signal line 64. The necessary information is given to the unit 4, and as a result, address translation is performed.

Along with this, information necessary for address translation is stored in the address translation unit 4.

The buffer unit 5 stores a copy of a portion of the information in the main memory unit 6 in such a manner that the address on the main memory where the information is stored can be identified. If the unit 5 has information corresponding to the actual address of the instruction sent via the signal line 45, it reads this information and sends it to the instruction decoding operand address generation unit 2 via the signal line 52. send to If there is no corresponding information (mishit), the unit 5 sends the Bonreiji address to the main memory unit 6 via the signal line 56, and the main memory unit 6
reads out a series of information including the information at the address and sends it to the buffer unit 5 via the signal line 65, and at the same time transfers the information at the address to the unit 2 via the signal line 62. The unit 5 stores a series of information transferred from the unit 6 in a form whose addresses on the main memory are known. The information storage capacity of the unit 5 is smaller than that of the unit 6, and the information stored in the unit 5 is a partial copy of the unit 6. The information stored in the unit 5 is changed when new information is transferred from the unit 6 but the unit 5 is already full of information, or when the information stored in the unit 5 is When a part or all of the information needs to be invalidated, part or all of the information of the unit 5 is erased from the unit 5 according to rules individually defined in the system. The instruction decoding operand address generation unit 2 decodes the instruction given via the signal line 52 or 62, generates an operand address (hereinafter referred to as data logical address) specified by the instruction, and transfers the generated address to the signal line. 24 to the unit 4. As in the case of instructions, said unit 4 converts the data into a logical address and sends it to said unit 5 via signal line 45.
If the relevant information is in the unit 5, the unit 5 sends it to the arithmetic and control unit 3 via the signal line 53.
If not, the actual data address is sent to the unit 6 via the signal line 56, and the unit 6 reads out a series of information including the corresponding information and sends it to the unit 5 via the signal line 65. The information is sent to the arithmetic and control unit 3 via.

The unit 3 is connected to the unit via a signal line 23.

Command information sent from port 2 and signal line 53 or 63
Perform calculations based on the information sent from.

When the unit 3 further requires information in the main memory, the data logical address is sent to the unit 4 via the signal line 34, and then sent to the signal line 53 through the same process as described above.
Or obtain information from the unit 5 or 6 via 63.

FIG. 2 is a diagram showing a more detailed example of the configuration of FIG. 1, which shows an example of the prior art. Boxes surrounded by double lines represent registers, which operate in synchronization with clock pulses. The dotted line boxes represent each unit 1, 2, 3, etc. in Figure 1.
Corresponds to 4, 5 and 6.

The instruction read control unit 1 has an instruction address register 101i containing an instruction logical address. , the instruction decoding operand address generation unit includes an instruction register 201 for storing instructions, an instruction decoding means 202 for decoding the instructions, an index memory 203 for storing an index specified by the instruction, and a memory for pace address modification. a base address memory 204 storing modification information;
A first operand generation means 205 mainly including a carry save adder, etc., and a register 20 that temporarily stores the result.
6, and a second operand generation means 207 mainly consisting of an adder that ultimately generates a data logical address. The address conversion unit 4 also includes a logical address register 401 that temporarily stores logical addresses of instructions and data.
The buffer unit 5 has a real address register 501 that temporarily stores instructions and data addresses, and an address translation means 402 that effectively realizes the function of an associative memory. It has a memory 502 that realizes the functions, and a local register 503 that is an output register thereof. The flow of information is as follows: instruction address register 101 → logical add register 4 old → address register 501 → local register 503 → instruction register 201 → register 206 → logical address register 401 →... If the clock pulse advances every one clock pulse, there will be a conflict between the signals applied to the logical address register 401 via the signal lines 14 and 24, so pipeline control that advances the flow of information every one clock pulse or every seven clock pulses is not possible. Therefore, the first feature of the present invention is that, as shown in FIG. 3, the address conversion unit 4 and buffer unit 5 in FIG. 2 are divided into one for instructions and one for data. The purpose of this technology is to eliminate conflicts between the information provided through the network, and to enable the flow of information to proceed one clock at a time through line control.

A second feature of the present invention is that the buffer units for instructions and data have the same capacity. That is, the instruction address conversion means 4021 of FIG. 3 used in the first execution column
, data address conversion means 4022, a circuit (not shown) that converts the logical address of the instruction and the operand into a real address, and a signal line 4 when there is no conversion information.
It has a circuit (not shown) that accesses the main memory 22 and the main memory 22 and 22 through signal lines 62 and 461, respectively, and obtains information necessary for conversion through signal lines 642 and 641. Third
In the figure, 4011, 4012, 5011, and 5012 are a logical address register for instructions and a real address register for data, respectively.

These are a real address register for instructions and a real address register for data.

Since the instruction buffer 5021 stores instructions, when an instruction logical address is given via the signal line 14, if the instruction buffer 5021 has the relevant information, the information can be stored in the instruction local register 5031. Further, the data buffer 5022 is connected to the instruction Hara hoop 5021.
Since the operand information is stored in the data local register 5032, if the logical address of the operand is given via the signal line 24, the data register 5022 stores the information in the data local register 5032. I can do it.

If there is no relevant information in the instruction buffer 5021 or data buffer 5022, each real address is sent to the main memory unit 6 via the signal line 562 or 561, and the relevant information or a series of information including it is sent to the entire signal line 652 or 651.
Get from. At this time, as shown in FIG. 2, the relevant information may be sent from the main memory unit 6 to the units 2 and 3 via an information transfer path other than the signal line 652 or 651. Furthermore, signal lines 561 and 562, signal line 6
51 and 652 may be the same information transfer path. Generally, the logical address given from the signal line 14 indicates a command word, but the logical address given from the signal line 24 may indicate not only a data word but also a command word. For example, an operand address in a branch instruction is an example. In this way, even if it is an operand address, when it is known that it indicates an instruction word, the information from the signal line 24 is transferred to the logical instruction address register by the discriminating means 403 as illustrated in FIG. You can also send it to 4011. However, in this case, although there is a conflict with the information from the signal line 14, the frequency is small and not every tarlock pulse. Here, signal lines 561, 562.651.652.461
, 462.641 and 642 need not be the main memory. For example, as shown in FIG. 5, it may be a secondary buffer 7 unit 7 placed between the buffer unit 5 and the main memory unit 6.

In general, the address conversion unit 4 converts the instruction shown in FIG. 3 into an address on the main memory using the start logical address field 4011Ae402 of the segment or page, as shown in FIG.
One specific address within the segment or page that is moved to field 011A is field 4, which indicates the deviation from the first address (hereinafter referred to as displacement).
011B, and this field is transferred to field 5011B of register 5011 without conversion. Instructions and data are segmented or paged. Therefore, when the segment t or page switches, the logical address is converted to a real address, and if this real address is written i;(t L, then the displacement 4012 is used until the next segment or page switches. You can know the address just by giving .Therefore,
As in the second embodiment of the present invention shown in FIG.
12.degree. buffers 5021 and 5022 and local registers 5031 and 5032 each have one for instructions and one for data, and the respective logical addresses of instructions and takes are used to store segments/takes for knowing whether a segment or page switching has occurred. Page switching detection means 40
7 and 406, the information on signal lines 14 and 24 is switched by selectors 405 and 404. When there is no segment or page change, signal lines 1.42 and 24
2 through each of the instruction real address register 2 and the address register 50.
11 and the data real address register 5012. When the segment or page is switched, the logical segment/page address of the instruction or data is sent to the logical address register 401 via signal lines 141 and 241, respectively. The error address of the instruction or data, which is sent to the real address register 5011 or 5012 and then converted into a real segment/page address via the converting means 402, is stored in the real address register 5011 or 5012. At the same time, displacement is sent from each of the signal lines 142 or 242. In this case, if information is simultaneously transferred from the signal lines 14 and 24, contention will occur, but this will occur very rarely.

In the case of FIG. 7, when handling even information from the signal line 24 as reading a command word, as shown in FIG. An output provided via signal line 45 can be provided to the instruction real address register via signal line 452, and a signal provided via signal line 242 may be provided via signal line 243, respectively. In this case and the operation shown in FIG. 3 with the means shown in FIG. 4, the operand address pointed to an instruction, so the instruction buffer 5o21 was accessed. Instruction local register 50
31 to the third distribution means 50 as shown in FIG.
42 can be sent to the unit) 31C.

When accessing from the unit 3 to the address translation unit 4 and buffer unit 5, the instruction read control unit 1 and the instruction decoding operand address generation unit 2 are also used.
In the same way as the contention with the above unit 1 and 2, there is a conflict with the access from the unit 1 and 2, but the main memory read from the unit 3 is mainly a decimal type instruction, and from the perspective of the frequency, it is due to the access from the unit 1 and 2. It's not as serious as the competition. Access from unit 3 may be handled in the same way as access from unit 2 according to the present invention.

The effectiveness of the instruction buffer 5021 and data buffer 5022 depends not only on their capacity and control method, but also on the characteristics of the program (dynamic address changes, etc.).

A publication published by IBM in 1968 in 5021 (I
BM Systems Journal) Vol.
7 No., I J, pages 15 to 21, J
- Paper by S. Liptay “Structural Aspects of the System 360 Model 85
-II @ The Emperor Cache (5tructualaspe
cts of the System / 360M
odel 85 II The cache ) J g
Assuming the use of the cache of a self-installed IBM system 360, however, when instructions and data are stored in the same cache in a fully associative manner (hereinafter referred to as a shared cache)
Analyzing the miss rate of a cache with separate caches for instructions and data (hereinafter referred to as a split cache), it was found that when a shared cache was divided equally into instructions and data, it was The miss rate of the split type cache is equal to or lower than that of the shared type cache, and even if it increases in very rare cases, it is expected to be about 10 to 20%.

The rate at which an increase in cache miss rate contributes to an increase in the average instruction execution time of the central processing unit is (increase rate of cache miss rate) x (ratio of effective memory access time to average instruction execution time), and rate 10
The ~20% increase is reduced to a few percent increase in average instruction execution time. On the other hand, even with a cache capacity of 16 kilobytes, the cache generally has the longest inter-clock pulse logic delay time that determines the clock pulse interval of the central processing unit, and this tendency becomes stronger as the cache capacity increases. This is because the physical expansion of the memory array of the cache causes signal delays in the signal propagation medium, signal delays due to the increase in the number of drive gates due to the increase in the number of drivers driving the memory array, and signal delays due to the increase in the number of drive gates due to the increase in the number of drivers that drive the memory array. The main problem is signal delay due to an increase in the number of gate circuits to be selected.

Therefore, if one cache is divided into two equal parts, the logic delay time between clock pulses in the cache will be reduced, but the effect will not be maximized unless the cache is divided into equal capacities.・From this, even if the average instruction central row time increases by several percent due to an increase in the miss rate in a divided cache, it can be compensated for by shortening the clock pulse time by dividing the cache equally.

In the above embodiments, all the instruction buffers and data buffers of the present invention are configured to have the same capacity, but even if they are configured to have approximately the same capacity, the performance of the processing device can be improved. This approximately equal capacity means that the difference between the instruction buffer and the data buffer is within 255A.

That is, a feature of the present invention is that in a central processing unit that is highly pipeline controlled, read-out of instructions and data causes contention in the address translation unit 4 or buffer unit 5, so the address translation unit 4 or buffer unit 5 is The purpose is to divide the data into a range of equal capacity or approximately equal capacity as described above. Therefore, the use of components of this embodiment that are not related to the characteristics of the present invention does not particularly limit the scope of the present invention.

``-, The buffer unit has a capacity of 64 kilobytes in recent ultra-large machines, and there is a tendency for the capacity to increase as the main memory capacity increases with the development of memory element technology.

On the other hand, the address translation unit (y) has a capacity of about 100 to 500 words, which is two orders of magnitude smaller than the capacity of the buffer unit. Therefore, when the address conversion unit for instructions and data is divided, even if the capacity is twice that of the case where it is not divided, it is not comparable in cost to the case where the buffer unit 'f is twice as large.

By using the present invention, it is possible to deeply control the pipeline of a medium-heat processing unit, provide a good buffer memory miss rate for a wide range of program characteristics, shorten the clock interval, and as a result improve the performance of the central processing unit. improvement can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional data processing device, FIG. 2 is a diagram showing the detailed configuration of FIG. 1, FIG. 3 is a diagram showing a first embodiment of the present invention, and FIG. FIG. 5 is a diagram showing an example of applying the present invention; FIG. 6 is a diagram showing a logical process of converting a logical address into a real address; FIG. The figure shows a second embodiment of the present invention, FIG. 8 shows a partial modification of the device in FIG. 7, and FIG. 9 shows a partial modification of FIGS. 3 and 7. FIG. In FIGS. 1 to 9, l...instruction succession/control unit, 2...instruction decoding/operand address generation unit, 3...arithmetic control unit, 4...address conversion unit, 5... - Buffer unit, 6... Main memory unit, 7... Secondary buffer unit, 14.
23, 24, 34, 45, 46, 52, 53, 56, 6
2゜63, 64, 65...Signal line, 101-
...Instruction address register, 201...Instruction register, 202...Instruction decoding means, 203...Index memory, 204...Pace address memory, 205,
207... Operand address generation means, 206...
Register, 401... - Ring address register, 402
. . . address conversion means, 403 . . . determination means, 40
6,405...Selector, 406.407'...Segment/page switching detection means-501...Real address register, 5o2 Buffer memo! J, 503...Local register. Agent Patent Attorney Susumu Uchihara■ ゛・、・－ノ' 3rd, 4th, 5th

Claims (1)

[Claims] (IJ) A storage means for storing instructions and data, and a plurality of reading means for reading out the stored contents of the storage means. An instruction storage for storing a copy of a part of the instructions stored in the storage means. means, data storage means having a storage capacity that is the same as or substantially the same as the storage capacity of the instruction storage means and storing a copy of a part of the data stored in the storage means, and one of the plurality of reading means. an instruction address converter stage which converts the logical address into a real address of the storage means when a logical address of an instruction is given from one of the plurality of reading means and provides the conversion result to the instruction storage means; and one of the plurality of reading means. and data address conversion means for converting the logical address into a real address of the storage means when a logical address of data is given from one reading means and providing the conversion result to the data storage means. (2) a storage means for storing instructions and data; a plurality of reading means for reading out the contents of the storage means; and an instruction storage means for storing a copy of a part of the instructions stored in the storage means; data storage means having a storage capacity that is the same as or substantially the same as the storage capacity of the instruction storage means and stores a copy of a part of the data stored in the storage means; and one reading means of the plurality of reading means. an instruction logical address detection means for detecting whether or not a logical address of an instruction given from the instruction exceeds a segment/page boundary, and if the logical address does not exceed a segment/page boundary, directly providing at least a part of the logical address to the instruction storage means; address converting means for converting the logical address into an address of the storage means when the means detects that the logical address crosses a segment/page boundary and providing the conversion result to the instruction storage means; and among the plurality of reading means. data logical address detecting means for detecting whether or not a logical address of data given from one reading means of the data storage means exceeds a segment/page boundary; comprising: when the data logical address detection means detects that the logical address crosses a segment/page boundary, the address conversion means converts the logical address into a real address of the storage means and provides the conversion result to the data storage means; A data processing device according to claim 1, characterized in that: