JPS6076360A - Heat-sensitive recording device - Google Patents

Heat-sensitive recording device

Info

Publication number
JPS6076360A
JPS6076360A JP18476883A JP18476883A JPS6076360A JP S6076360 A JPS6076360 A JP S6076360A JP 18476883 A JP18476883 A JP 18476883A JP 18476883 A JP18476883 A JP 18476883A JP S6076360 A JPS6076360 A JP S6076360A
Authority
JP
Japan
Prior art keywords
circuit
signal
recording
recording signal
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18476883A
Other languages
Japanese (ja)
Inventor
Yoshihiko Sato
佐藤 恵彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP18476883A priority Critical patent/JPS6076360A/en
Publication of JPS6076360A publication Critical patent/JPS6076360A/en
Pending legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/315Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
    • B41J2/32Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
    • B41J2/375Protection arrangements against overheating

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To enable the prevention of heat accumulation in heating resistors, by providing a larger number of recording signal information storage circuits than the number of heating bodies, by comparing recording signal informations at the current time point with those before the number of the heating bodies, and by controlling a time of electrification based on the result of comparison. CONSTITUTION:Heating resistors 31 in the number of 1728, for instance, are connected, half and half, to an external power source 32 through terminals (a) and (b). A recording signal input from a terminal 35 is inputted in series alternately for each of the terminals (a) and (b), enters an 864-bit shift register 38, and is read out through an inverter 40. Meanwhile, the content holding recording signals for half a line is outputted in parallel and transferred to latch circuits 41, 43 and 45 sequentially. The content of the latch circuit 45 is passed through a NAND circuit 48 controlled by a printing signal E and is compared with the content of the latch circuit 41 in an AND circuit 49, and the result of comparison enters a driving circuit 33. A time of electrification of the heating resistors is controlled according to the result of comparison. In this way, the number of LSI can be halved, and a printing density can be controlled to be uniform.

Description

【発明の詳細な説明】 本発明は、信頼度が高く低価格で而も高速記録の可能な
サーマルヘッドに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thermal head that is highly reliable, inexpensive, and capable of high-speed recording.

f −−rルヘッドは、記録素子である発熱抵抗体を一
列に多数並べ、これらの発熱抵抗体を選択的に通電発熱
させて感熱記録紙に印字記録するものである。このサー
マルヘッドを用いたファクシ電り装置は、価格が安く保
守運用費が少なく、而も画像情報を高品質で印字記録で
きるために、ここ数年来急速に普及してきている。
The f--r head has a large number of heat-generating resistors, which are recording elements, arranged in a row, and selectively energizes these heat-generating resistors to generate heat to print and record on thermal recording paper. Facsimile machines using this thermal head have rapidly become popular over the past few years because they are inexpensive, require low maintenance and operation costs, and can print and record image information with high quality.

このサーマルヘッドは、例えば第1図に示す構成図によ
り形成されている。ここで、1は感熱記録用の発熱抵抗
体であシ、例えば8本1fiの密度で配置されたA4判
相当のサーマルヘッドの場合は、合計1728本の抵抗
体が一列にヘッド基板上に並設される。これらの発熱抵
抗体1の各一端は各部電源2の一端に共通接続され、各
他端は発熱抵抗体1と同数の駆動回路3をそれぞれ介し
て電源2の他端に接続されている。
This thermal head is formed according to the configuration diagram shown in FIG. 1, for example. Here, 1 is a heating resistor for thermal recording. For example, in the case of a thermal head equivalent to A4 size in which 8 resistors are arranged at a density of 1fi, a total of 1728 resistors are arranged in a row on the head substrate. will be established. One end of each of these heating resistors 1 is commonly connected to one end of a power source 2 for each section, and each other end is connected to the other end of the power source 2 via the same number of drive circuits 3 as the heating resistors 1.

駆動回路3はスイッチング素子を主体として構成され、
ラッチ回路を介して並列に供給される記録信号と、出力
制御信号4を介して入力される出力許可信号り、との一
致出力によって各スイッチング素子がオン動作し、各々
発熱抵抗体1に個別に通電を行なう。
The drive circuit 3 is mainly composed of switching elements,
When the recording signal supplied in parallel via the latch circuit and the output permission signal input via the output control signal 4 coincide with each other, each switching element is turned on, and each switching element is individually connected to the heating resistor 1. Turn on electricity.

5は記録信号入力端子であり、ことばは例えば1ライン
IJ)1728ビツトの白黒2値のファクタB)画像信
号等の一連の記録信号が直列に入力される。この記録信
号は、タイミング制御端子6から入力されるタイオング
信号8.によって制御されるANDゲート7およびOR
ゲート8を順次介して、第1の記憶回路であるシフトレ
ジスタ9に入力される。このシフトレジスタ9は172
8ビツトの容量を有し、クロック入力端子10から入力
されるクロック信号Cpによシ、入力された記録信号を
順次右方に転送して1ライン分記憶する。シフトレジス
タ9の内容は並列に出力され、1728個のラッチ回路
11にラッチ制御端子12へのラッチトリが信号Tt、
のタイミングで移される。
Reference numeral 5 denotes a recording signal input terminal, into which a series of recording signals such as words (for example, one line IJ), a 1728-bit black and white binary factor B) image signal, etc. is input in series. This recording signal is a tie-on signal 8. input from the timing control terminal 6. AND gate 7 and OR controlled by
The signals are inputted sequentially through gates 8 to a shift register 9, which is a first storage circuit. This shift register 9 is 172
It has an 8-bit capacity, and according to the clock signal Cp input from the clock input terminal 10, the input recording signal is sequentially transferred to the right and stored for one line. The contents of the shift register 9 are output in parallel, and the latch signal to the latch control terminal 12 is sent to the 1728 latch circuits 11 by the signal Tt,
It will be moved at the timing of.

しかしこの方法によるサーマルヘッドにおいては、同じ
発裂抵抗体に対応する記録信号が2ライン以上連続して
有意情報(黒情報)の場合、つまシ同じ発熱抵抗体に数
2イン連続して通電を行なった場合には、その発熱抵抗
体は熱の蓄積による過熱状態によって記録印字の濃度を
異常に高めたり、あるいは発熱抵抗体自体が破壊するお
それがあった。
However, in the thermal head using this method, if the recording signal corresponding to the same exploding resistor is significant information (black information) for two or more consecutive lines, the same heating resistor is energized several times in succession. If this is done, there is a risk that the heating resistor may become overheated due to heat accumulation, causing the density of the recorded print to become abnormally high, or that the heating resistor itself may be destroyed.

そこで異常印字記録あるいは抵抗体の破壊を防止するた
めに種々の対策が考えられている。その一つに駆動回路
に供給される現時点での一連の記録信号と、1時刻前の
記搬信号との情報を相対応するビット毎に比較し、その
比較結果に応じて駆動回路による発熱抵抗体への通電時
間を制御する方式がある。これは以下の方法によって実
現することができる。
Therefore, various measures have been considered to prevent abnormal printing or destruction of the resistor. One of them is to compare the information between the current series of recording signals supplied to the drive circuit and the recorded signal one time ago for each corresponding bit, and depending on the comparison result, the heat generation resistance by the drive circuit is There is a method to control the time that electricity is applied to the body. This can be achieved by the following method.

すなわち、シフトレジスタ9の内容を右端の終段から直
列に読出し、タイミング制御端子13から入力されるタ
イミング信号S鵞によって制御されるANDゲート14
を介して、第2の記憶回路であるもう一つのシフトレジ
スタ15に入力する。
That is, the contents of the shift register 9 are read out in series from the rightmost final stage, and the AND gate 14 is controlled by the timing signal S input from the timing control terminal 13.
is input to another shift register 15, which is a second storage circuit.

このシフトレジスタ15はシフトレジスタ9と同じ17
28ビツトの容量を有し、タイ2ング信号Smによって
制御されるANDゲート21を介して入力されるクロッ
ク信号により、入力された記録信号を順次右方に転送し
て記憶する。
This shift register 15 is the same as shift register 9.
It has a capacity of 28 bits and is sequentially transferred to the right to store the inputted recording signals by a clock signal inputted through an AND gate 21 controlled by a timing signal Sm.

シフトレジスタ15の内容は右端の終段から直列に読出
されて、比較回路16でシフトレジスタ9から直列に読
出された記録信号と比較される。
The contents of the shift register 15 are serially read out from the rightmost final stage, and compared with the recording signal serially read out from the shift register 9 in a comparator circuit 16.

この比較回路16は、シフトレジスタ15の直列出力を
反転するインバータ17およびこのインバータ17の出
力とシフトレジスタ9の直列出力との一致信号を得るA
NDゲート18で構成される。
This comparison circuit 16 includes an inverter 17 that inverts the serial output of the shift register 15 and an A that obtains a coincidence signal between the output of the inverter 17 and the serial output of the shift register 9.
It is composed of an ND gate 18.

そして、この比較回路16の出力はタイヤング信号S、
のインバータ19による反転信号で制御されるANDゲ
ート20およびORゲート8を順次介して、シフトレジ
スタ9に置換データとして入力される。
The output of this comparison circuit 16 is the tireing signal S,
The data is input to the shift register 9 as replacement data through an AND gate 20 and an OR gate 8 which are controlled by an inverted signal from an inverter 19.

5− このようにして各発熱抵抗体に連続して通電を行なわせ
る場合には、連続せずに通電を行なう場合よシも通電時
間を短かくする制御が可能となる。
5- When each heat generating resistor is energized continuously in this manner, it is possible to control the energization time to be shorter than when the energization is performed non-continuously.

しかし、この方式は発熱抵抗体本数に相当する駆動回路
またはスイッチング素子を必要とした。
However, this method requires drive circuits or switching elements corresponding to the number of heating resistors.

これらのスイッチング素子は32素子をもりて1個のL
SIに形成され、ワイヤボンディング等の手段により、
1素子毎に対応する発熱抵抗体に接続される。従って、
1728本の発熱抵抗体が形成されているサーマルヘッ
ドの場合には54個のLSIと、少なくとも1728本
のワイヤボンディング数わ必要とした。製造されるサー
マルヘッドの信頼度はワイヤポンディング数に反比例す
るために、ワイヤボンディング数が多い従来のサーマル
ヘッドは信頼度の低いものとなることは避けられなかっ
た。を九所要とするL8Iの数量が54個と多いことは
、サーマルヘッドの価格低減に対する障害となっていた
These switching elements have 32 elements to form one L
formed on the SI, and by means such as wire bonding,
Each element is connected to a corresponding heating resistor. Therefore,
In the case of a thermal head in which 1728 heating resistors are formed, 54 LSIs and at least 1728 wire bondings are required. Since the reliability of a manufactured thermal head is inversely proportional to the number of wire bondings, it was inevitable that conventional thermal heads with a large number of wire bondings would have low reliability. The large quantity of 54 pieces of L8I, which requires nine pieces, has been an obstacle to reducing the price of thermal heads.

これらの点は、より高い解像度の画像を必要とする場合
に顕著となった。すなわち、現在の8本6− /Hの解像度から12本/ muあるいは16本/酊の
解像度になると、所要とするワイヤボンディング数はA
4判相当の場合に、それぞれ2560本あるいは345
6本となるものであった。また所要とするLSI数はそ
れぞれ80個あるいは108個となるものであった。そ
れ故、製造されるサーマルヘッドは信頼度の保障が事実
上不可能になり而も高価とならざるを得なかった。
These points became more noticeable when higher resolution images were required. In other words, if the current resolution of 8 wires/mu or 16 wires/mu is increased, the required number of wire bonding will be A.
2560 or 345 pieces each for 4-size equivalent
There were six pieces. Further, the required number of LSIs was 80 or 108, respectively. Therefore, it is virtually impossible to guarantee the reliability of the manufactured thermal heads, and they have to be expensive.

従って本発明は、所要とするLSI数およびワイヤボン
ディング本数を従来の半分以下とするこができ、しかも
印字濃度を均一に制御することができるサーマルヘッド
を提供することにあシ、低置で而も高信頼度のサーマル
ヘッドを提供するととkある。
Therefore, it is an object of the present invention to provide a thermal head that can reduce the required number of LSIs and wire bonding to less than half of the conventional number, and can uniformly control printing density. The company also claims to provide highly reliable thermal heads.

本発明は、駆動回路に接続される発熱抵抗体数を複数と
し、記録信号情報を記憶する記憶回路を前記発熱体数よ
りも1つ以上多い個数設け、現時点で記録すべき記録信
号情報と、前記発熱体本数前の記録信号情報とを比較す
る比較回路を設けることVC特徴がある。
The present invention provides a plurality of heating resistors connected to a drive circuit, a memory circuit for storing recording signal information that is one or more more than the number of heating elements, and recording signal information to be recorded at the present time, A VC feature is that a comparison circuit is provided to compare the recorded signal information with the number of heating elements before.

以下第2図を参照して本発明の詳細な説明する。The present invention will be described in detail below with reference to FIG.

31は発熱抵抗体であり1例えは8本/酩の解像度のA
4版相当のサーマルヘッドの場合、1728本が一列に
ヘッド基板上に並設される。この内半数の864本がa
端子に共通接続され、残〕半数の抵抗体が共通にb端子
に接続される。a端子及びb端子は外部電源32の一端
にスイッチ機構SWを通して交互に接続される。a端子
及びb端子に接続された1対の発熱抵抗体の他端は共通
に単一の駆動回路に接続される。従って駆動回路33と
しては従来の半分864個が必要となり、画然ながら所
要とするワイヤボンディング数は生滅する。これらの駆
動回路を介した発熱抵抗体の他端は[源32の他端に共
通に接続される。
31 is a heating resistor, and one example is A with a resolution of 8 wires/drink.
In the case of a thermal head equivalent to the 4th edition, 1728 thermal heads are arranged in a row on the head substrate. Half of these, 864, are a
The remaining half of the resistors are commonly connected to the b terminal. The a terminal and the b terminal are alternately connected to one end of the external power supply 32 through a switch mechanism SW. The other ends of the pair of heating resistors connected to the a and b terminals are commonly connected to a single drive circuit. Therefore, the number of drive circuits 33 required is 864, which is half of the conventional number, and the number of required wire bondings is obviously reduced. The other ends of the heating resistors via these drive circuits are commonly connected to the other end of the source 32.

35は記録信号入力端子であり、ここには例えはa端子
忙接続された発熱抵抗体に相当する864ビツトの画像
信号等の一連の記録信号を直列に入力する。次に所定の
時刻後にb端子に接続された発熱抵抗体に相当する86
4ビツトの記録信号を直列に入力する。以下この繰シ返
しを行なう。これらの記録信号は、タイミング制御信号
端子36から入力されるタインング信号Sによって制御
されるANDゲート37を介してシフトレジスタ38に
入力される。このシフトレジスタは864ビツトの容量
を有し、りpツク入力端子39から入力されるクロック
信号cPによシ、入力された記録信号を順次右方に転送
して、記録信号をインバータ40を介して外部に読出す
Reference numeral 35 denotes a recording signal input terminal, into which a series of recording signals, such as an 864-bit image signal corresponding to a heating resistor connected to the a terminal, is input in series. Next, after a predetermined time, 86 corresponding to the heating resistor connected to the b terminal
A 4-bit recording signal is input in series. This process is repeated from now on. These recording signals are input to the shift register 38 via an AND gate 37 controlled by a timing signal S input from a timing control signal terminal 36. This shift register has a capacity of 864 bits, and sequentially transfers the input recording signal to the right according to the clock signal cP input from the input terminal 39, and transfers the recording signal via the inverter 40. and read externally.

1ラインの半分の記録信号(例えばa端子に接続された
発熱抵抗に相当する記録信号)を収容したシフトレジス
タ38の内容は並列に出力され、864ビツトに相当す
る回路で構成された第1のラッチ回路41にラッチ制御
端子42の2ツテトリがT、のタイミングで移される。
The contents of the shift register 38, which accommodates half of the recording signal of one line (for example, the recording signal corresponding to the heating resistor connected to the a terminal), are output in parallel, and the contents of the shift register 38, which accommodates the recording signal of half of one line (for example, the recording signal corresponding to the heating resistor connected to the a terminal), are output in parallel to the first shift register, which is composed of a circuit corresponding to 864 bits. Two transfers of the latch control terminal 42 are transferred to the latch circuit 41 at timing T.

ラッチ回路41の内容は、ラッチ制御端子44のラッチ
トリがT。
The contents of the latch circuit 41 are such that the latch signal of the latch control terminal 44 is T.

のタイミングで、第2のラッチ回路43に並列に転送さ
れる。同様に、ラッチ回路43の内容は、ラッチ制御端
子46のラッチトリが1口のタイミングで、第3のラッ
チ回路45に転送される。これ9− らのラッチ回路は全て864ビツトの容量を有する。
The signals are transferred in parallel to the second latch circuit 43 at the timing of . Similarly, the contents of the latch circuit 43 are transferred to the third latch circuit 45 at the timing of one latch entry of the latch control terminal 46. All nine latch circuits have a capacity of 864 bits.

第3のラッチ回路45の内容は並列に出力され、印字時
間制御端子47の印字信号Eによって制御されるNAN
Dゲート48を介して、第1のラッチ回路41の並列出
力とともにANDゲート49に加わり、相対応するピッ
ト毎に記録情報が比較される。ANDゲートの出力は駆
動回路33に並列に転送さn、出力制御信号34を介し
て入力される出力許可信号りとの一致出力によって各ス
イッチング素子がオン動作し、各々発熱抵抗体31に個
別に通電を行なう。
The contents of the third latch circuit 45 are output in parallel and are controlled by the print signal E of the print time control terminal 47.
It is applied to an AND gate 49 together with the parallel output of the first latch circuit 41 via a D gate 48, and recorded information is compared for each corresponding pit. The output of the AND gate is transferred in parallel to the drive circuit 33, and each switching element is turned on by a coincidence output with the output permission signal inputted via the output control signal 34, and each switching element is individually connected to the heating resistor 31. Turn on electricity.

従って本発明は、発熱抵抗体の駆動回路33に供給され
る現時点での一連の記録信号と、二時刻曲の記録信号と
の情報な相対応するビット毎に比較し、その比較結果に
応じて駆動回路による発熱抵抗体への通電時間を制御す
ることができるために、高速駆動可能なサーマルヘッド
とすることができる。
Accordingly, the present invention compares the current series of recording signals supplied to the heating resistor drive circuit 33 with the recording signal of the two-time tune for each corresponding bit, and according to the comparison result. Since the driving circuit can control the time during which the heating resistor is energized, the thermal head can be driven at high speed.

次に、との夾施例の動作を第3図のタイムチャ10− −トを参照して説明する。Next, the operation of the interpolation example with time chart 10- This will be explained with reference to

まず、初期状態としてラッチ回路41,43.45の内
容はいずれもオール″O”とする。この状態で記録信号
入力端子35に、半ライン相当の記録信号(a端子に接
続された発熱抵抗体に相当する記録信号)が直列に入力
されてきたとする。このとき、タイミング制御端子36
には第3図(a)に示すように端子35に864ビツト
の記録信号が入力されている間、1”レバルのタイミン
グ信号島が継続して入力されている。従って記録信号は
ゲート37を通電し、クロック信号CPによシフトレジ
スタ38に読込まれる。
First, as an initial state, the contents of the latch circuits 41, 43, and 45 are all set to "O". In this state, it is assumed that a recording signal equivalent to half a line (a recording signal corresponding to the heating resistor connected to the a terminal) is input in series to the recording signal input terminal 35. At this time, the timing control terminal 36
As shown in FIG. 3(a), while the 864-bit recording signal is input to the terminal 35, the timing signal island of 1" level is continuously input. Therefore, the recording signal is input to the gate 37. The signal is energized and read into the shift register 38 by the clock signal CP.

シフトレジスタ38に半247分(a端子接続発熱抵抗
体相当分)の記録信号が全て読込まれると、第3のラッ
チ回路45に端子46を介して第3図(b)に示すラッ
チトリが信号Tsが供給される。
When all the recording signals for half 247 minutes (corresponding to the heating resistor connected to the a terminal) are read into the shift register 38, the latch signal shown in FIG. 3(b) is sent to the third latch circuit 45 via the terminal 46. Ts is supplied.

このためICCノツチ路43の内容即ちII OIIが
そのtま並列にラッチ回路45にラッチされる。次に第
2のラッチ回路43に端子44を介して第3図(e)に
示すラッチトリが信号T、が供給される。このためにラ
ッチ回路41の内容即ち′O”がそのまま並列にラッチ
回路43にラッチされる。最後に第1のラッチ回路41
に端子42を介して第3図(d)に示すラッチ) IJ
が信号T、が供給される。このために、シフトレジスタ
38に読込まれた配録信号(a端子接続発熱抵抗体相当
の記録信号)がラッチ回路41にそのまま並列にラッチ
される。
Therefore, the contents of the ICC notch path 43, ie, IIOII, are latched in the latch circuit 45 in parallel until that time. Next, a latch signal T shown in FIG. 3(e) is supplied to the second latch circuit 43 via the terminal 44. For this purpose, the contents of the latch circuit 41, ie 'O', are latched as they are in the latch circuit 43 in parallel.Finally, the first latch circuit 41
IJ via the terminal 42 (the latch shown in FIG. 3(d))
is supplied with a signal T. For this reason, the distribution signal read into the shift register 38 (recording signal corresponding to the heating resistor connected to the a terminal) is latched in parallel to the latch circuit 41 as it is.

このとき印字時間制御端子47の印字信号Eは10”と
し、電源32の8WはaIIC接続されている。従って
比較回路50のNANDゲート48の出力は常に51”
であシ、ラッチ回路41から並列に読出される記録信号
はそのままANDゲート50を通過する。
At this time, the print signal E of the print time control terminal 47 is set to 10", and the 8W of the power supply 32 is connected to the aIIC. Therefore, the output of the NAND gate 48 of the comparator circuit 50 is always 51".
Otherwise, the recording signals read out in parallel from the latch circuit 41 pass through the AND gate 50 as they are.

ラッチトリが信号T1の直後、第3図(e)に示すよう
に駆動回路33に端子34を介してtなるパルス幅の出
力許可信号り、が供給される。これによって、駆動回路
33はラッチ回路41から記録信号として1″つtヤ黒
情報が与えられているもののみスイッチング素子がtの
時間だけオン勧化し、a端子に接続された発熱抵抗体3
1に通電を行なう。通電終了後、電源のSW端子はb端
子側に切換えられる。
Immediately after the latch signal T1, an output enable signal with a pulse width of t is supplied to the drive circuit 33 via the terminal 34, as shown in FIG. 3(e). As a result, the drive circuit 33 turns on the switching element only for the time t to which the latch circuit 41 has given the recording signal 1'' black information, and the heating resistor 3 connected to the a terminal
1 is energized. After the energization ends, the SW terminal of the power supply is switched to the b terminal side.

一方、シフトレジスタ38にはその内容がラッチ回路4
1にラッチされた後に、クロックパルスcPによってb
端子接続抵抗相当分の記録信号が直列忙転送される。こ
の間端子36にはタイミング信号8.として1”が継続
して入力される。記録信号が全て読込まれると、前と同
様の操作によシ、ラッチ回路45にはオール″on、ラ
ッチ回路43には″a端子接続抵抗相尚分の記録信号”
、ラッチ回路41には″′b端子接続抵抗相肖分の記録
信号”がラッチされる。b端子接続抵抗相当分の記録信
号は駆動回路34を介してtなるパルス幅の出力許可信
号り、によってスイッチング素子を動作させ、黒情報が
与えられている発熱抵抗体にのみ印字記録される。その
後電源のSW端子はa端子側に切換られる、これら一連
の操作によって12イン相轟分の印字記録が完了する。
On the other hand, the contents of the shift register 38 are stored in the latch circuit 4.
After being latched to 1, b
Recording signals corresponding to the terminal connection resistance are serially transferred. During this time, the timing signal 8. 1" is continuously input as 1". When all the recording signals are read, the same operation as before is performed, and the latch circuit 45 is all "on", and the latch circuit 43 is set to "a terminal connected resistance phase." Minute recording signal”
, the latch circuit 41 latches the ``record signal of the proportion of the resistance connected to the b terminal''. The recording signal corresponding to the resistance connected to the b terminal is sent via the drive circuit 34 to an output permission signal with a pulse width of t, which operates the switching element, and prints and records only on the heating resistor to which black information is given. Thereafter, the SW terminal of the power supply is switched to the a terminal side, and by this series of operations, the print recording for the 12-inch phase is completed.

次に第2ライン目の記録のためにa端子接続抵抗相当分
の記録信号がタイミング信号S、&C工って13− シフトレジスタ38に読込まれる。その後ラッチトリが
Ts、 T雪、TIによって、ラッチ回路45には″′
第1ラインのa端子接続抵抗相当分の記録信号″が読込
まれ、ラッチ回路43には″第1ラインのb端子接続抵
抗相当分の記録信号′°が読込まれ、ラッチ回路41に
は1第2ラインのa端子接続抵抗分の記録信号′°が読
込まれる。従って比較回路50はラッチ回路4Bの内容
とラッチ回路41の内容とを比較することができる。即
ち、a端子接続抵抗相当分の第1ラインの記録1B号と
第25)インの記録信号とを相対応するビット毎に比較
することができる。
Next, for recording the second line, a recording signal corresponding to the resistance connected to the a terminal is read into the shift register 38 using the timing signals S, &C. After that, the latch circuit 45 receives ``'' due to the latch trigger Ts, T snow, and TI.
A recording signal equivalent to the resistance connected to the a terminal of the first line is read into the latch circuit 43, a recording signal corresponding to the resistance connected to the b terminal of the first line is read into the latch circuit 43, and a recording signal corresponding to the resistance connected to the b terminal of the first line is read into the latch circuit 41. The recording signal '° corresponding to the resistance connected to the a terminal of the two lines is read. Therefore, the comparison circuit 50 can compare the contents of the latch circuit 4B and the contents of the latch circuit 41. That is, it is possible to compare the recording signal No. 1B of the first line and the recording signal of the 25th line corresponding to the resistance connected to the a terminal for each corresponding bit.

ラッチ回路41にラッチされた第22インの記録信号は
、比較回路50のNANLIゲート端子47の印字時間
制御信号″が0′”のときにのみANDゲート49をそ
のまま通過することができ、出力許可信号り、によって
駆動回路33のスイッチング素子を動作させ、黒情報即
ち′1″が与えられている発熱抵抗体にのみ印字記録さ
せる。しかし印字時間制御端子47の信号E、がt3時
間11″の=14− ときKは、第1ラインの記録信号が60”、即ち白情報
のときだけNANDゲート48の出力が1″となシ、第
2のラインの記録信号がANDゲート49を通過するこ
とができる。
The recording signal of the 22nd input latched by the latch circuit 41 can pass through the AND gate 49 as it is only when the printing time control signal ``of the NANLI gate terminal 47 of the comparison circuit 50 is 0'', and output is permitted. The switching element of the drive circuit 33 is operated by the signal E, and printing is performed only on the heating resistor to which the black information, that is, '1'' is given. = 14-, then K means that the output of the NAND gate 48 is 1'' only when the first line recording signal is 60'', that is, white information, and the second line recording signal passes through the AND gate 49. I can do it.

従ってtなる時間の出力杆可信号D3が与えられた駆動
回路33のスイッチング素子に12水準のオン動作時間
が与えられることになる。即ち、第1ラインの画信号が
白のときには1時間発熱抵抗体が通電過熱される。しか
し第1ラインの画信号が黒のときVC1′!、1.=1
−1.時間(1,< 1 )発熱抵抗体が通電過熱され
る。
Therefore, the switching element of the drive circuit 33 to which the output enable signal D3 of time t is applied is given 12 levels of on-operation time. That is, when the image signal of the first line is white, the heating resistor is energized and heated for one hour. However, when the picture signal of the first line is black, VC1'! , 1. =1
-1. The heating resistor is energized and heated for a time (1, < 1).

このように本発明によれば、記録信号の同じビットに連
続し7て@l 1 mが現われ、同じ発熱抵抗体が2ラ
イン以上連続して通電される場合、その発熱抵抗体への
1回の通電時間は、2回目以降においては通常のtの時
間より短いt!の時間となるので1.の値を適当に定め
ることによシ、発熱抵抗体の熱の蓄積を防止することが
できる。
As described above, according to the present invention, when @l 1 m appears consecutively in the same bit of the recording signal and the same heating resistor is energized for two or more lines in succession, the heating resistor is energized once. The energization time of t! is shorter than the normal time of t from the second time onwards. 1. By appropriately determining the value of , it is possible to prevent heat from accumulating in the heating resistor.

また、通電時間を常に一定とする方式と比較して、より
短い通電休止時間のもとで発熱抵抗体の過熱を防止でき
るために、本発明によるサーマルヘッドは高速記録を行
なうことが可能である。
Furthermore, compared to a method in which the energization time is always constant, overheating of the heating resistor can be prevented with a shorter energization stop time, so the thermal head according to the present invention can perform high-speed recording. .

さらに本発明によれば、現ラインの記録信号と相対応す
る前ラインの記録信号とを相対応するビット毎に比較し
、その比較結果により発熱抵抗体への通電時間な制御す
るため、同じ発熱抵抗体に対して連続せずに通電を行な
う場合の通電時間tと、連続して通電する場合の通電時
間t、とを各々独立VC選ぶことができる。このためt
、とじて発熱抵抗体の過熱を防止でき、譲度ムラを生じ
ないような最適の時間を選ぶことが可能である。
Further, according to the present invention, the recording signal of the current line and the recording signal of the corresponding previous line are compared for each corresponding bit, and the time of energization of the heating resistor is controlled based on the comparison result. The energization time t when the resistor is energized non-continuously and the energization time t when the resistor is energized continuously can be selected by independent VCs. For this reason, t
, it is possible to select an optimal time that prevents overheating of the heating resistor and does not cause uneven yield.

また、前期比較回路において現ラインの記録信号と相対
応する前ラインの記録信号とを相対応するビット毎に比
較する場合には、例えば駆動回路に2本の発熱抵抗体が
接紗されているときには、n回目の記録信号と!l−2
回目の記録信号即ち2段前の記録信号とを比較すればよ
い。従って駆動回路にrn本の互に独立する発熱抵抗体
が接続されている場合には、n回目の記録信号とn−m
回目の記録信号とを比較すればよいことは当然である。
In addition, when comparing the recording signal of the current line and the corresponding recording signal of the previous line for each corresponding bit in the previous comparison circuit, for example, two heating resistors are attached to the drive circuit. Sometimes, the nth recorded signal! l-2
It is only necessary to compare the recorded signal of the second time, that is, the recorded signal of two stages before. Therefore, if rn mutually independent heating resistors are connected to the drive circuit, the n-th recording signal and n-m
It goes without saying that it is only necessary to compare the recorded signal for the first time.

この場合ICは少なくとも(m+i)段の記録信号を記
1意するラッチ回路あるいはシフトレジスタ等の機能が
LSIに必要とされる。
In this case, the IC requires a function such as a latch circuit or a shift register for recording at least (m+i) stages of recording signals.

1また、本発明は上記の効果を呈する以上、棟々変形し
て実施が可能である。すなわち前記実施例においては、
相対応する現ラインと前ラインの記fI&信号情報を比
較することによって各発熱抵抗体への通を時間を制御し
たが、前記比較結果によって通電rgl数を変えるとし
為う手法を採用してもよい。
1. Furthermore, since the present invention exhibits the above-mentioned effects, it can be implemented with various modifications. That is, in the above embodiment,
Although the time of conduction to each heating resistor was controlled by comparing the fI & signal information of the corresponding current line and the previous line, the method of changing the number of energized rgl depending on the comparison result would not work. good.

又、通電時間は予め複数種類設定しておくこともで哀る
。更に、’l’、 、 ’i’、 、 T、等の信号は
一本の端子から分離回路を通して供給することもできる
。また、例えばa端子接続抵抗相当分の印字を複数のブ
ロックに分割して奥行すゐこともできる。
Moreover, it is also a problem to set a plurality of types of energization time in advance. Furthermore, signals such as 'l', 'i', 'T', etc. can be supplied from a single terminal through a separation circuit. Further, for example, printing corresponding to the a terminal connection resistance can be divided into a plurality of blocks to increase the depth.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の感熱記録装置を示すブロック図、第2図
は本発明の実施例を示すブロック図、第3図は第2図の
装置の動作を説明する図である。 31・・・・・・発熱抵抗体、32・・・・・・電源、
33・・・・・・17− 駆動回路、38・・・・・・シフトレジスタ、41・・
・・・・第1のラッチ回路(第1の記憶回路)、43・
・・・・・第2のラッチ回路(第2の記憶回路)、45
・・・・・・第3のラッチ回路(第3の記憶回路)、5
0・・・・・・比較回路。 18−
FIG. 1 is a block diagram showing a conventional thermal recording device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram explaining the operation of the device shown in FIG. 2. 31... Heating resistor, 32... Power supply,
33...17- Drive circuit, 38...Shift register, 41...
...first latch circuit (first storage circuit), 43.
...Second latch circuit (second storage circuit), 45
...Third latch circuit (third storage circuit), 5
0... Comparison circuit. 18-

Claims (1)

【特許請求の範囲】[Claims] 少なくとも2つの群に分割され而も一列に並設された発
熱抵抗体と、これら各群から抽出された発熱抵抗体が複
数本単一の駆動回路に接続され而も分割された群毎に一
連の記録信号に応じて選択的に尚該群に属する発熱抵抗
体に通電を行なわしめる駆動回路と、これらの駆動回路
に供給すべき一連の記録信号情報を記憶する前記分割数
プラス1個以上の記憶回路と、第1の記憶回路に記憶さ
れた記録信号情報と前記群数に対応する時刻前の記録信
号情報とを相対応するビット毎に比較する比較回路と、
この比較回路の比較結果によシ前記発熱抵抗体への通電
時間あるいは通電回数をその発熱抵抗に対し連続して通
電が行なわれる場合には連続せずに通電が行なわれる場
合よシも短かくあるいは少なくなるように制御する通電
時間制御手段とを真備することを%黴とする感熱記録装
置。
Heat-generating resistors are divided into at least two groups and arranged in a row, and a plurality of heat-generating resistors extracted from each group are connected to a single drive circuit. a drive circuit that selectively energizes the heat-generating resistors belonging to the group in accordance with the recording signal of the group; and a drive circuit that stores a series of recording signal information to be supplied to these drive circuits, the number of divisions plus one or more. a storage circuit; a comparison circuit that compares the recorded signal information stored in the first storage circuit with the recorded signal information before the time corresponding to the number of groups for each corresponding bit;
Depending on the comparison result of this comparison circuit, the time or number of times of energization to the heat generating resistor will be shorter when the heat generating resistor is energized continuously than when energized non-continuously. Alternatively, the thermal recording device is equipped with an energization time control means to control the amount of mold.
JP18476883A 1983-10-03 1983-10-03 Heat-sensitive recording device Pending JPS6076360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18476883A JPS6076360A (en) 1983-10-03 1983-10-03 Heat-sensitive recording device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18476883A JPS6076360A (en) 1983-10-03 1983-10-03 Heat-sensitive recording device

Publications (1)

Publication Number Publication Date
JPS6076360A true JPS6076360A (en) 1985-04-30

Family

ID=16158980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18476883A Pending JPS6076360A (en) 1983-10-03 1983-10-03 Heat-sensitive recording device

Country Status (1)

Country Link
JP (1) JPS6076360A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6230062A (en) * 1985-07-31 1987-02-09 Seiko Epson Corp thermal printer
JPS63302074A (en) * 1987-01-28 1988-12-08 Seiko Epson Corp Thermal printer printing control device
US5153650A (en) * 1990-04-27 1992-10-06 Mita Industrial Co., Ltd. Toner container and process unit including the same
US5585894A (en) * 1987-02-26 1996-12-17 Canon Kabushiki Kaisha Process cartridge with a movable image bearing member as well as a contactable member, and an image forming apparatus having the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6230062A (en) * 1985-07-31 1987-02-09 Seiko Epson Corp thermal printer
JPS63302074A (en) * 1987-01-28 1988-12-08 Seiko Epson Corp Thermal printer printing control device
US5585894A (en) * 1987-02-26 1996-12-17 Canon Kabushiki Kaisha Process cartridge with a movable image bearing member as well as a contactable member, and an image forming apparatus having the same
US5153650A (en) * 1990-04-27 1992-10-06 Mita Industrial Co., Ltd. Toner container and process unit including the same

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