JPS6076455U - absolute value circuit - Google Patents
absolute value circuitInfo
- Publication number
- JPS6076455U JPS6076455U JP16492783U JP16492783U JPS6076455U JP S6076455 U JPS6076455 U JP S6076455U JP 16492783 U JP16492783 U JP 16492783U JP 16492783 U JP16492783 U JP 16492783U JP S6076455 U JPS6076455 U JP S6076455U
- Authority
- JP
- Japan
- Prior art keywords
- diode
- input terminal
- anode
- inverting input
- cathode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の絶対値回路の実施例を示すブロック図、
第2図は本考案の一実施例を示すブロック図、第3図お
よび第4図は第2図の実施例の動作を示す説明図、第5
図は本考案の他の実施例を示すブロック図である。
1・・・入力端、4・・・共通電位点、5・・・出力端
、Q□9 QI Q3・・・演算増幅器、D3.D、・
・・ダイオード。FIG. 1 is a block diagram showing an example of a conventional absolute value circuit.
FIG. 2 is a block diagram showing an embodiment of the present invention, FIGS. 3 and 4 are explanatory diagrams showing the operation of the embodiment of FIG. 2, and FIG.
The figure is a block diagram showing another embodiment of the present invention. 1... Input end, 4... Common potential point, 5... Output end, Q□9 QI Q3... Operational amplifier, D3. D.・
··diode.
Claims (1)
オードのアノード(又はカソード)とを接続して直流電
流信号の入力端とし、前記第1ダイオードのアノード(
又はカソード)を演算増幅器の反転入力端に接続し、前
記第2ダイオ−“ドのカソード(又はアノード)を前記
演算増幅器の非反転入力端に接続し、前記演算増幅器の
出力端と前記反転入力端との間に抵抗を接続し、前記非
反転入力端と共通電位点との間を抵抗で接続して成る直
流電流信号の絶対値回路。The cathode (or anode) of the first diode and the anode (or cathode) of the second diode are connected to form an input terminal for a DC current signal, and the anode (or anode) of the first diode is connected to the anode (or cathode) of the second diode.
or the cathode) of the second diode is connected to the inverting input terminal of the operational amplifier, the cathode (or anode) of the second diode is connected to the non-inverting input terminal of the operational amplifier, and the output terminal of the operational amplifier and the inverting input terminal of the second diode are connected to the non-inverting input terminal of the operational amplifier. An absolute value circuit for a direct current signal, comprising a resistor connected between the non-inverting input terminal and a common potential point, and a resistor connected between the non-inverting input terminal and a common potential point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16492783U JPS6076455U (en) | 1983-10-25 | 1983-10-25 | absolute value circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16492783U JPS6076455U (en) | 1983-10-25 | 1983-10-25 | absolute value circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6076455U true JPS6076455U (en) | 1985-05-28 |
Family
ID=30361455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16492783U Pending JPS6076455U (en) | 1983-10-25 | 1983-10-25 | absolute value circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6076455U (en) |
-
1983
- 1983-10-25 JP JP16492783U patent/JPS6076455U/en active Pending
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