JPS6079882U - television receiver - Google Patents

television receiver

Info

Publication number
JPS6079882U
JPS6079882U JP17203883U JP17203883U JPS6079882U JP S6079882 U JPS6079882 U JP S6079882U JP 17203883 U JP17203883 U JP 17203883U JP 17203883 U JP17203883 U JP 17203883U JP S6079882 U JPS6079882 U JP S6079882U
Authority
JP
Japan
Prior art keywords
television receiver
vertical
read out
picture tube
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17203883U
Other languages
Japanese (ja)
Inventor
康成 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP17203883U priority Critical patent/JPS6079882U/en
Publication of JPS6079882U publication Critical patent/JPS6079882U/en
Pending legal-status Critical Current

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  • Television Systems (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第３図は夫々従来例を示す構成図、第２図及
び第４図は夫々従来例の説明のための図、第５図は本考
案の一実施例の説明のための図、第６図は本考案の一実
施例を示す構成図、第７図はその説明のための図、第８
図は本考案の他の実施例を示す構成図である。 ４は映像検波回路、９は受像管、１６は変換回路、１６
ａ及び１６ｂは夫々フィールドメモリ、１７はコントロ
ール回路である。1 and 3 are configuration diagrams showing a conventional example, FIG. 2 and 4 are diagrams for explaining the conventional example, respectively, and FIG. 5 is a diagram for explaining an embodiment of the present invention. , FIG. 6 is a configuration diagram showing an embodiment of the present invention, FIG. 7 is a diagram for explaining the same, and FIG.
The figure is a configuration diagram showing another embodiment of the present invention. 4 is a video detection circuit, 9 is a picture tube, 16 is a conversion circuit, 16
A and 16b are field memories, respectively, and 17 is a control circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ２：１のインターレース方式の映像信号を受信しフィー
ルドメモリに書き込んだ後倍の速度で読み出して受像管
に印加し、上記受像管を倍の速度の水平及び垂直偏向周
波数で偏向すると共に垂直、偏向を制御して上記フィー
ルドメモリから読み出される垂直周期単位毎の信号が上
記映像信号の水平走査間隔の　だけ順次シフトして４：
１のインターレース走査をするようにしたことを特徴と
するテレビジョン受像機。After receiving a 2:1 interlaced video signal and writing it into the field memory, it is read out at twice the speed and applied to the picture tube, and the picture tube is deflected at the horizontal and vertical deflection frequencies of the double speed, as well as vertical and deflection. The signal read out from the field memory in each vertical period unit is sequentially shifted by the horizontal scanning interval of the video signal by controlling 4:
1. A television receiver characterized by performing interlaced scanning.
JP17203883U 1983-11-07 1983-11-07 television receiver Pending JPS6079882U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17203883U JPS6079882U (en) 1983-11-07 1983-11-07 television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17203883U JPS6079882U (en) 1983-11-07 1983-11-07 television receiver

Publications (1)

Publication Number Publication Date
JPS6079882U true JPS6079882U (en) 1985-06-03

Family

ID=30375122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17203883U Pending JPS6079882U (en) 1983-11-07 1983-11-07 television receiver

Country Status (1)

Country Link
JP (1) JPS6079882U (en)

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