JPS6087533A - Frequency selection circuit for radio communication equipment - Google Patents

Abstract

PURPOSE:To attain addition/subtraction of an operating frequency in an optional unit by providing a digit register, an addition/subtraction pulse transmission means and a digit designation means in a frequency selection circuit for radio communication equipment. CONSTITUTION:A digit designation button 17 on an operation panel 1 is depressed and the operating position is moved sequentially from the least significant bit to the most significant bit by a digit designation ring counter Qa. The designated digit is displayed on a display device 2. In depressing a frequency selection addition button 16, an addition pulse is fed to a terminal U of the digit register Q via a designated switch among digit designation switches S1 S9. In depressing once a frequency selection subtraction button 15 similarly, one subtraction pulse to a terminal D of the digit register Q is fed. The counter value of digit registers Q1 Q9 is displayed on the display device 2. The operting frequency is selected with the operating method having the same logical structure independently of the increment/decrement unit of the operating frequency so as to improve the operability.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency selection circuit for a radio communication device, and more particularly to a frequency selection circuit for a radio communication device that selects an operating frequency without using a mechanical operating member such as a frequency selection dial.

As shown in FIG. 1, a conventional frequency selection circuit for a radio communication device has a frequency selection dial 3 (
There is also a main dial (also called the main dial). The frequency selection dial 3 is composed of a rotating body that can be rotated clockwise or counterclockwise. The variable amount of the selected frequency in one rotation of the frequency selection dial 3 is determined by the combination of the on/off settings of the megahertz button 4 and the fine button 5. Normal rotation or reversal of the frequency selection dial 3 is detected by using a light beam passing through a plurality of slits provided in the peripheral part. The light passing through the slit is detected by a light receiving element, and normal rotation and reverse rotation are distinguished depending on the detection order. Frequency selection dial 3. Megahertz button 4. Fine button 5. Clarifier button (clarifier, operation...
・Operation method for making the receiving frequency variable with respect to the transmitting frequency)
As shown in the figure, the frequency division ratio setting circuit 9 consisting of a pulse integration counter takes a counted value according to the operation.The frequency division ratio setting circuit 9
The count value set in is output as frequency division information to the program side terminal of the programmable counter 10a that divides the frequency of the oscillation signal output from the voltage controlled oscillator 10e of the PLL circuit 10-. Programmable counter 1
The oscillation signal frequency-divided by 0a is phase-compared with the reference signal output from the reference signal oscillator 10b in the phase comparator 10c, and an error signal according to the comparison is output to the voltage-controlled oscillator 10e via the low-pass filter 10d. . The voltage controlled oscillator 10e is locked when it oscillates with an oscillation signal corresponding to the frequency division information. The oscillation signal is sent to mixer 1 which determines the operating frequency.
If the operating frequency is the receiving frequency, the received signal from the antenna 11 via the RF unit 12 is converted into a predetermined intermediate frequency.

The converted intermediate frequency is sent to the intermediate frequency circuit 14. Further, the selected operating frequency is displayed on the display 2. Note that the frequency division information of the frequency division ratio setting circuit 9 can also be set directly digitally by operating the numeric buttons @= and * and the megahertz unit setting button Ka provided on the frequency setting keyboard 8. Reference numerals 24 to 31 in FIG. 1 are on/off switches, which switch the meter when power is connected/disconnected when transmitting, RF amplifier switch, RF attenuator on/off, speech processor on/off, noise blanker on/off, AGC time constant speed/slow switching, transmission/reception switching, vOX operation is harmful
It is marked with l. In addition, operation mode (radio wave type 4SS
BL side, 5SB-U side, cw wide, cw narrow, A M -
FM) e-memory channel (address that stores information such as operating frequency), AF gain volume, RF
First gain yJ? For information on each of the 7 functions related to IJ Neem, M'El Dine Control, Drive Control, Squelch Volume, Noise Blanket Volume, Should Volume, ■F Shift Volume, IF Width Volume, etc., press 7 function buttons 2 and 1.
Specify the desired 7-point setting by operating the function lamp '1. It is generated by a pulse integration counter corresponding to s -1,n. The count value of the designated pulse integration counter is set by the count i4 generated by operating the addition button 22 and the subtraction button 23. The setting amount is displayed on display 2 &
Display in .

In general, since the radio wave format and broadcast frequency are fixed in the receiving circuit for broadcast waves, etc., the desired radio wave is automatically selected and
It is possible to correct detuning using a figure-8 curve or the like.

However, 5. In radio communication devices applied to amateur radio, etc., the reception conditions for the desired radio waves are complex, so delicate operations that cannot be quantified are required to maintain the selection of the operating frequency, eliminate visitor radio waves, noise, etc. The results are monitored by auditory sensations, which are difficult to measure. For this reason, even other wireless communication devices in which variable resistance elements or the like are digitized have the disadvantage that the frequency selection dial cannot be converted into a button.

The present invention has been made in view of the above points, and an object of the present invention is to provide a frequency selection circuit for a wireless communication device that does not use a disc-shaped operating member such as a frequency selection dial.

The frequency selection circuit for a radio communication device according to the present invention is provided with registers for the first, second, . A digit specifying means for specifying this digit register is provided, and addition A? is generated in response to the operation of the frequency setting addition button or the frequency setting subtraction button to the digit register specified by the digit specifying means. A pulse or subtraction pulse is sent to set the desired count value.

Hereinafter, one embodiment of the frequency selection circuit for a radio communication device according to the present invention will be described based on FIGS. 3 and 4.

3 and 4. Components that are the same in FIGS. 1 and 2 are denoted by the same reference numerals, so their explanation will be omitted.

In FIG. 3, %Q s ""Qn is a digit register. (For the sake of explanation, n is assumed to be 9.) Digit register Q1 is for the 1st place, I Hz year unit, digit register Qz is for the 2nd place, 10 Hz year unit...Digit register Q9 is for the 9th place. It operates in 100 MHz units. For example, the digit register Q2 for the second screen does not perform an addition operation when an addition/4 pulse is input to the U terminal, and when it is OK from 9, the product register Q3 for the upper third digit Outputs a carry pulse to

When the subtraction base pulse is input to the D terminal, the subtraction operation is not performed, and when the value goes from 1 to 0, the product register Q for the lower 1st place is used.
Lower digit to 1 J? Output the route.

Q and L are ring counters for specifying digits. When the digit designation button 17 is pressed, the digit designation ring counter Qa increments and sequentially moves its active position from the least significant bit (hereinafter referred to as LSB) to the most significant bit (hereinafter referred to as MSB). The LSB is connected to the control side terminals of the 9th digit designation switches S9 and 89'; and S1'.

The digit designation switches 5l-s,' are formed by normally open contacts, and for example, when the LSB becomes active, the digit designation switch S and 811
' operates and the normally open contact is closed. Further, the designated digit is displayed on the display 2. When the frequency selection addition button 16 provided on the operating knob 1 is pressed once, an addition pulse is sent to the U terminal of the product register Q9 via the closed normally open contact of the digit designation switch S9. When the frequency selection reduction button 15 is pressed once, one addition pulse is sent to the D terminal of the register Q via the closed normally open contact of the digit designation switch S9. Subtraction button 1 for frequency selection
If the 5 or frequency selection addition button 16 is kept pressed, the cycle of the addition/4' pulse or subtraction pulse changes depending on the length of time it is pressed.

The count values of the product registers Q1 to Q9 are displayed on a display 2 formed of liquid crystal or the like. Product registers Q1 to Q9
The count value can also be set by operating the numeric buttons Ko~ and the Oyohimekahertz setting button Ka on the keyboard 8 provided on the operation panel 1.

The count values of the product registers Ql-Qll are sent as frequency division information to the log 2 block counter 10m of the PLL circuit.

Here, it is assumed that the operating frequency is 430.726 MHz. The digit designation button 17 is operated to designate the product sostar Q-, and the frequency selection addition button 16 is used to set the count value of the product register Q1 to 4. Set 30726 sequentially.

The last "6." is Nosta Q4 for 4th place.

The second digit register Qq or Ql is used for fine adjustment. FIG. 5 is another example of the frequency selection circuit for a wireless communication device according to the present invention. D1 to D9 are non-lock type digit selection buttons. Digit selection button ~D9 is digit designation switch S1 + S'
l~S9h Provided corresponding to S'9, for example, when the digit selection button D9 is pressed once, the digit designation switch 5918'9
operates, and the normally open contact is closed. The operating state is indicated by a mark such as an arrow below the displayed number on Disgray 2. When the other digit selection buttons D to DI are pressed once, another digit is selected. When you press the digit selection button D-DI twice, 2
1. '1ffi Numbers above the pressed digit are locked, and numbers below are reset to zero.

To release the lock, for example, press the upper digit selection button D9. FIG. 6 is a front view of the operation AI nostril 1 shown in FIG. 5, and digit selection buttons D1 to D9 are provided below the display 2.

Ancillary circuits such as auto scan, manual scan, and tallariifier for searching received radio waves are based on conventional examples.

The 1st and 2nd digits are carried up and down depending on the subtraction.
・・・・・・Nth product register, 1st place, 2nd place...
...Addition/subtraction/Gurus sending means that outputs addition/subtraction/Gurus to the n-th product register, and No digit designation that specifies the digit to be calculated by the addition/subtraction pulse output from the addition/subtraction/9th pulse sending means. Since it has a configuration that includes means and, it has the feature that the operating frequency can be added or subtracted in arbitrary units. Therefore, regardless of the unit of increase/decrease in the operating frequency, the operating frequency can be selected using an operating method having the same logical structure, resulting in improved operability. Further, since no rotating members are used, the number of man-hours for installation, adjustment, etc. related to the mechanical structure can be reduced, and an improvement in the space factor on the operation panel can be expected.

[Brief explanation of the drawing]

Fig. 1 is a front view of the operation panel of a conventional frequency selection circuit for radio communication equipment, Fig. 2 is a pro-ref diagram of the conventional frequency selection circuit for radio communication equipment, and Fig. 3 is a frequency selection circuit for radio communication equipment according to the present invention. A block diagram showing one embodiment of the selection circuit, FIG. 4 is a surface view of the operation panel in FIG. 3, FIG. 5 is a block diagram showing another example of the selection circuit in FIG. It is a front view of e-nel. In the figure, l is the operation panel, 2 is f"
3 is a frequency selection dial, 4 is a megahertz button, 5 is a fine button, 6 is a clarifier button, 7 is a frequency selection operation member, 8 is a key, 9 is a frequency division ratio setting circuit, 10 is a P
LL circuit, 1OIL is programmable counter, 10b
is a reference signal oscillator, 10c is a phase comparator, lOd is a loaf filter, 10e is a voltage controlled oscillator, 11 is an antenna, 12 is an RF unit, 13 is a mixer, 14 is an intermediate frequency circuit, 15 is a frequency selection dial, 16 is the frequency selection dial, 17 is the digit designation button, D1 to D9 are the digit selection buttons, KO" is the numeric button, Ka is the megahertz unit setting button,
81~S/, is digit designation switch, QI~Q9 is product V
, ) star, and Aa are ring counters for specifying digits. Patent applicant Yaesu Musen Co., Ltd. Figure 1 Figure 2 Figure 1 0 Figure 3 Figure 4 Figure 1 Figure 5

Claims (1)

[Claims] 1. A PLL circuit consisting of a reference oscillator, a phase comparator, a low-pass filter, and a voltage-controlled oscillator, a programmable counter provided in the feedback path of the PLL circuit, and outputting branch information to the program terminal of the programmable counter. a frequency division ratio setting means for selecting an operating frequency according to an oscillation signal output from the voltage controlled oscillator; A register for the 1st, 1g, 2nd... Jth digit, an addition/subtraction pulse sending means for outputting the full output of addition/subtraction to the register for the 1st, 2nd,... nth digit, and the addition/subtraction / digit designation means for designating the digit to be counted by addition/subtraction pulses output from the base pulse sending means;
, and is configured to select an operating frequency using ninth frequency information according to the count value of the Zosta for the first place, 'second place, . . . nth place. frequency selection circuit.