JPS6089134A - Radio communication equipment - Google Patents

Abstract

PURPOSE:To clarify the logical structure among data and to improve the operability by setting a transmission/reception frequency with a frequency data obtained from a frequency adjusting means and a frequency data reading means in a radio equipment having a memory. CONSTITUTION:In operation address designation buttons M1-Mn, an address data corresponding to frequency adjusting means D1-D9, 19, 20 at present is preserved and the frequency data related to the address data is prepared as a transmission frequency. The frequency data of the address data designated by the address designation buttons M1-Mn is read to a register 27 of the frequency adjusting means. In operating the frequency adjusting means D1-D9, 19, 20 in this state, a memory 18 is brought into the write operation, the frequency data during adjustment is written in the area of data of the designated address and becomes the frequency data at the reception side.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wireless communication device, and more particularly to a wireless communication device having a memory for storing transmission frequencies and reception frequencies.

Conventionally, a wireless communication device has a memory 18, as shown in FIG.
There is a wireless communication device that stores operational data such as B-U side, CW/wide, K/narrow, AM, FM, etc. The frequency data to be written is adjusted by a frequency adjustment means including a frequency adjustment dial 15, an up button 15a, a down button 15b, a frequency division ratio setting circuit 11, etc. provided on the operation panel 13, and is specified by the memory selection dial 17. Written to the data area of the address. The frequency data stored in the memory 18 (hereinafter referred to as memory frequency data) and the frequency data generated by the frequency division ratio setting circuit 11 (hereinafter referred to as adjusted frequency data) are data bus switched according to the operation of the memory recall key 14 or the like. The output signal is sent to the log 2 maple counter 9 of the PLL circuit 4 via the input device 10. When it is desired to change the memory frequency data, the user operates the reset button 16 and the memory selection dial 17 to reset the desired memory frequency data to the frequency division ratio setting circuit 11 in advance via the data bus 18'a. There is no essential difference between the memory frequency data and the adjustment frequency data, except for whether or not they can support the frequency adjustment function on the transmitting/receiving circuit side. On the transmitting/receiving circuit side, it is desirable that frequency data for transmitting and frequency data for receiving are always selectively prepared, and that both can be finely adjusted, that the transmitting and receiving frequencies can be reversed, and that the same transmitting and receiving frequencies can be used. However, in the actual circuit, the button for specifying the change range per rotation of the frequency adjustment dial 15, the upper W
(A band selection dial etc. is provided for specifying the numerical value of the z part.Also, there is a device in which numeric buttons corresponding to O to 9 are provided in the - key code 12 so that the numerical value of the frequency division ratio setting circuit 11 can be directly set. There is a transmitting/receiving frequency selection circuit that forms memory frequency data with a storage means such as a register and selects this storage means with a rotary switch.In this case, two rotary switches are provided and the frequency data selected by each rotary switch is selected. A changeover switch is provided to determine whether it is used for transmission or reception.If the new terminal of the changeover switch is connected to the frequency adjustment means such as the frequency adjustment dial 15 via the transmission or reception switch. Frequency adjustment function is obtained during transmitting or receiving operations.

The above-mentioned conventional wireless communication device uses a frequency adjustment dial as a means of generating frequency data (some inconvenience (combined with a band selection means for correction)), and also has some inconvenience (for correction) for fine adjustment. The frequency adjustment dial is also used for transmitting and adjusting frequency data for sexual intercourse. For this reason, frequency data is generated directly on the frequency data generation means using numeric buttons, etc.
Alternatively, even if already formed frequency data is obtained from a memory etc., it is only convenient enough to omit the generation of pan r information corresponding to the upper digits, etc., and has the disadvantage that the logical structure of the data cannot be clarified. 0 For this reason, operation/? The flannel is equipped with QIS material strength X for each minor operation.J, l;
,, has drawbacks such as poor workmanship, complicated circuit configuration, and large number of parts. The purpose of the present invention is to plan and provide a free communication device that clarifies the 6≦rational structure between the frequency data generated by the frequency adjustment means.

Hama I, who defines the memory according to the present invention, 2nd. Addressing means consisting of an n-th addressing button or the like is provided. When an address designation means such as an address designation button is operated, address data corresponding to the frequency adjustment function is currently saved and frequency data related to this address data is prepared as one frequency for transmission. Frequency data of the address data designated by the address designation button is read out to the frequency adjustment means. If the frequency adjustment means is operated in this state, the memory will be in an intrusion operation.Frequency adjustment means "T: The frequency data being adjusted should be transferred to the data area of the specified address.The frequency data being adjusted is The data is configured to be the frequency signal data on the receiving side.

Hereinafter, one embodiment of a wireless communication device according to the present invention will be described with reference to the drawings.

Components that are the same in FIG. 3, FIG. 1, and FIG. 2 are designated by the same reference numerals, so any explanation will be omitted.

In FIG. 3, the frequency adjustment means consists of digit designation buttons D-D (n is assumed to be 9 for explanation), frequency selection 1 n subtraction button 19, frequency selection addition bit 20, and adjustment frequency data generation register 27. It is configured.

The adjustment frequency data generation register 27 includes a first-place digit register Q1, a second-place digit register Q2, etc. shown in FIG.
Digit register Q for 0th place.

(For the sake of explanation, n is 9) Formed by digit designation button 1)
The digit registers Q1 to Q specified by -D are 9. Addition button 20 for frequency selection or subtraction button 19 for frequency selection
Count the addition, subtraction, and yals output according to the operation of 9.
When returning from 0 to 0, use upper digit register Q -Q9
To carry/return from l to 0, use 91~
IB-force Noculus to Q8. For digits/ZOSTA Q
1 to Q0 become the register 27 for generating adjustment frequency data. The count values organized in the digit registers Q1-Q become adjustable frequency data, that is, adjustable frequency data, and are outputted to the data bus switch 10 via the data bus 10IL.

M1 to M are address designation buttons. Address specification button M
, ~ When MfL is created, the addressing side OR circuit 24m
operates and transfers the contents of the 9111 address register 23a to the storage address register 23b.

The frequency data transfer means for the frequency adjustment means is composed of a memory control circuit 25a for the working side address register and a working side address register 23&.

By operating the address designation buttons M1 to MtL, the contents of the current address register 23& are transferred to the storage address register, and furthermore, the contents of the address specified by the storage address register are read to the memory frequency data register 28. Later, memory control circuit 2 for the address register on the active side
5a works.

When the current side address register memory control circuit 25a is activated, a control signal is sent to the RD terminal via the normally closed contact of the read/write changeover switch 26. When a control signal is sent to the RD terminal, the current side address register 23a
The frequency data stored in the data area of the address data specified by is read out and transferred to the adjustment frequency data generation ResosF 27.

The adjustment operation interlocking writing means is composed of a digit specifying side OR circuit 24d and a reading/writing changeover switch 26. When the digit designation buttons D1 to D9 are operated, the digit designation side OR circuit 24d
operates and sends a memory control signal to the WR terminal of the memory 18 via the closed normally open contact of the read/write changeover switch 26. When the memory control signal is input to the WR terminal of the memory 18, a write operation is performed, and the frequency data according to the count value of the adjustment frequency data generation register 27 is transferred to the data area of the address specified by the current side address register 23a on the data bus. 27a.

Frequency data reading means is storage address register 2
3 b, memory control circuit 2 for storage side address 9less register
5b and a memory frequency data register 28. When the address designation buttons M1 to MfL are operated and the address designation side OR circuit 24m operates, the contents of the current address register 23a are transferred to the storage address register 23b under the control of the register control circuit 23e. At the same time, the storage side address register memory control circuit 25b operates and sends a memory control signal to the RD terminal of the memory 18.

When the memory control '$4I signal is input to the RD terminal of the memory 18, the data at the address designated by the storage side address register 23b is read out to the memory frequency data register 28 via the data area 18a. After the read operation is completed, the operation sequence is passed to the current address register memory control circuit 25a.

The display 22 is formed of liquid crystal or CRT and has display areas M/1 to M'1 as shown in FIG. 4, and displays frequency data and operational data corresponding to the address designation buttons M1 to M7. Digit designation buttons, ~D, are placed directly below where the frequency data is displayed. Subtraction button 19 for frequency selection and addition button 2 for frequency selection
0 is placed near the digit designation button ~D. The upper two bits of the display area M/, ~M'Y are displayed as "00"rlOJrolJ or "11" in gray. If "00" is displayed, the data in the corresponding memory area is unused. It is shown that.

If the upper bit is 11, it is the adjustment frequency data.
The data in the corresponding memory area is rewritten according to the adjustment of the adjustment frequency data generation register 27. If the lower bit is “1”, memory frequency data register 1
It is being read to 0b. Numerals 33 to 40 in the figure are on/off switches that connect/disconnect the power, switch the meter during transmission, RF anzo switch, RF attenuator on/off, speech processor on/off, noise blanker on/off, AGC time constant slow switch, transmit/receive switch, vOX An operation has been assigned. Operation mode selection, AF gain, RF gain, volume, microphone dyne control, drive control, squelch, noise blanker threshold, volume, F shift, volume, engineering F width volume, etc. selection or functional control. For those that require, select each of the above functions.
The ring counter is driven by the pulse output by pressing the function selection button 30, and the desired value is input using the function up button 31 and the function down button 32 to the pulse integration counter determined by the value of the ring counter. By setting a numerical value, you can perform predetermined control.

The controlled amount is displayed on the display area 22f.

Further, reference numeral 41 is a meter.

Here, the display area M/1 associated with address 1 of the memory 18 is r Q 1 j r 50.420. ,
Q) lIHz J, display area M'2 related to address 2 is "10" r 50.540, 0) J (z J and display selection digit designation buttons D1 to D7, subtraction button 19 for frequency selection, frequency selection The frequency data of the display area M'2 changes in conjunction with the operation of the addition button 20.The adjusted frequency data is transferred between the data bus 10a, which is the child side of the data bus switch 1o, and the data bus 10ct-, which is the normally closed bus switching side. For example, the received frequency data is sent to the programmable counter 9 as reception frequency data.
controls the data path switch 10 by operating the zero transmission/reception changeover switch 30 provided on the slave data bus 10b, and switches the frequency data output via the slave data buses 10a and 10b to either transmission or reception. When address designation button M1 is pressed, display area M1' is set to V10.
J r 50.420. OMI (z J tona p-y
'Isplay area M2' is rolJ r50.540
．． OMHz J. At the same time, the contents of the adjustment frequency data generation register 27 are 50.420. It becomes OMHz.

Also, memory frequency data register 28 ki 50
．． 540. OMHZ. In other words, address designation button M
, and as soon as the data at the corresponding address is changed by operating M2, the frequency data in data areas 10m and 10b on the child side are read and retrieved. Furthermore, the data area of the memory 18 controlled by the adjustment frequency data generation register 27 has changed. The display area M'2 shows r 01 J r 50.420. When the memory specification button M2 is pressed again when OMH2J is selected, the upper bit becomes [1].
Changes with the moon. That is, the frequency data at address 2 of the memory 18 is read to the adjusted frequency data generation register 27, and a write operation is performed under the control of the adjustment operation of the adjusted frequency data generation register 27. However, the memory frequency data read into the memory frequency data register 28 is not subject to the adjustment operation. When the memory designation button M2 is pressed again, the upper pixel (rllJ) does not change, but the frequency data in the memory frequency data register 28 matches the adjusted one.

Although the above-described r-swivel 22 is provided with display areas M71 to M'1 corresponding to all addresses, only those corresponding to the adjustment frequency data and memory frequency data may be displayed.

The frequency data transfer means for the frequency adjustment means, the adjustment operation interlocking writing means, and the frequency data reading means may be obtained as functions of a microcomputer.The frequency adjustment means may be of a conventional dial type. In this case, it is necessary to provide a means for clarifying the point at which the adjustment operation starts.

When the address designation buttons M1 to Mn are formed by numerical buttons or rotary switches, means are provided for determining the address before the start of the designated action and the address at the end of the designated action.

The wireless communication device according to the present invention includes an address specifying means for specifying a memory address, and a transfer means for reading and transferring the contents of the memory immediately after the address is specified to the frequency adjusting means.
Adjustment operation interlocking writing means for writing the frequency data adjusted by the frequency adjustment means to an address immediately after the address is specified, and frequency data reading means for reading the frequency data written to the previously addressed memory. Since it has a single structure, it has the advantage that the write and read operation sequences are determined by address designation operations and frequency adjustment operations. This has the effect of simplifying the logical arrangement between the memory and the frequency adjustment means and improving operability. In addition, the number of operating parts can be reduced compared to the conventional one, and the number of operating parts can be reduced. It has the advantage that it can be applied to wireless communication equipment.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional wireless communication device with memory, Figure 2 is a block diagram of a conventional wireless communication device with memory.
The figure is a block diagram of a digitalized frequency adjustment means, FIG. 3 is a block diagram showing an embodiment of the wireless communication device according to the present invention, and FIG. 4 is a front view of the operation channel of FIG. 3. . Symbols in the figure: 1 is an antenna, 2 is a high-frequency amplifier circuit, 3 is a mixer, 4 is a PLL rotation 5 quasi-signal generator, 6 is a phase comparator, 7 is a low-pass filter, 8 is a voltage-controlled oscillator, 9
is a programmable counter, 10 is a data bus switch,
11 is a frequency division ratio setting circuit, 13 is an operation/tunnel, 14 is a memory call button, 15 is a frequency adjustment dial, 15a
is the up button, 1.5b is the down button, 16 is the reset button, 17a is the familiarization button, 17 is the memory selection dial, 1
8 is a memory, 19 is a subtraction button for frequency selection, 20 is an addition button for frequency selection, 21 is a keyboard, 22 is a display, 23a is a current address register, 23b is a storage address register, 23C is a register control circuit, and 24m is a Address specification side OR circuit, 14 & is digit specification side A circuit,
251L is a memory control circuit for the address register on the active side;
25b is a memory control circuit for storage side address register;
6 is a read/write changeover switch, 27 is a register for generating adjustment frequency data, 28 is a register for memory frequency-overtime, 30 is a function selection button, 31 is an up button for functions, 32 is a down button for functions.
33 to 40 are on/off switches, D and -D are digit designation buttons, M1 to Mn are memory designation buttons, Q and -Q are digit registers, and 81 to B/ are digit designation switches. Patent applicant Yaesu Musen Co., Ltd. Figure 1 Figure 3 Figure 4 Figure 4 1P

Claims (1)

[Claims] 1. A radio communication device 1 (or address designating means for designating the address of the memory; frequency data transfer means for frequency adjustment for transmitting the frequency from the data area of the address immediately after the address designated by the address designation means to the frequency adjustment means; adjustment operation interlocking writing means for writing the frequency data adjusted by the frequency adjustment means into the data area of the memory immediately after the frequency data has been addressed in response to the adjustment operation of the frequency adjustment means; (2) A radio communication device, comprising: a frequency data reading means for reading out the loaded frequency data, and configured to set a transmission/reception frequency using the frequency data obtained by the frequency adjusting means and the frequency data reading means.