JPS6089772A - Test system for integrated circuit element package unit - Google Patents

Abstract

PURPOSE:To improve the efficiency of fault detecting operation by selecting the application of a system clock in partial logical operation inserted between scan- in and -out operations in test mode in LSI unit. CONSTITUTION:A signal 0 is applied to a test mode signal terminal TM in normal logical mode and outputs of NANDs (a)-(n) are all 1, so ANDs aa-an are enabled to supply a system clock CLK to all LSIs 2a-2n. Then, data inputted to data input terminals PIa-PIr are processed synchronously with the CLK and outputted from data output terminals POa-POs. While TM is held at 1 in the scan in/out operation, only one of the NANDs (a)-(n) where the condition of NAND with a selection signal outputted by a decoder 3b is satisfied with a chip address signal from chip address signal terminals CADs (a)-(j) outputs 1.

Description

Detailed Description of the Invention (al) Technical Field of the Invention The present invention relates to an integrated circuit device (LSI) which is equipped with all logic functions of multiple units and has a scan-in/out function, or a printed wiring board equipped with a plurality of such devices. This invention relates to a test method using a circuit dividing means for rice (hereinafter referred to as P2 board).

(b) Background of technology In recent years, with the development of semiconductor technology, especially integration technology, LSIs that mount a large number of circuits in one package have become available at low cost. The Pt plate made of synthetic resin or ceramic plate that constitutes the block is 108sI.

Compared to the era when MSI was installed, it has become possible to realize much larger-scale logical functions. As the logic functions increase, the number of logic circuits accommodated in the same LSI and even the same PT board increases, and the number of programming and testing man-hours for tests such as levers continues to expand, making it possible to test the same PTAs all at once. is becoming increasingly difficult to implement. For this reason, a method is used in which a certain LSI on a PT board is focused on, and only the circuit portions involved in one or more data outputs and scan-out outputs, which are the output functions of the LSI, are divided into circuits and a partial test is performed.

The present invention relates to an improvement in a test method using a scan-in/out method and circuit dividing means.

fc) Prior Art and Problems Conventionally, when testing is performed using circuit dividing means, the scan-out output terminals and/or data output terminals to be focused on are limited to, for example, one LSI, and even if the logic circuits involved in the output are is connected to the front and rear (branch-like multiple stages) and extends to other series of LSIs.Therefore, the data obtained from the scan-out output terminal and/or data output terminal is subject to scan-in and scan-out operations. This is obtained as a result of the partial logic operation inserted in the question, but this partial logic 1 disturbance (1) operates according to the system clock like the logic operation in normal logic mode, so it is particularly difficult to use in dendritic multi-stage logic circuits. Since the number of FFs is large compared to the number of FFs or the number of stages within the LS 11 of interest, there is a high probability that racing will occur due to data delay, skew, and variation thereof, which may become an obstacle to failure detection.

(dl Object of the Invention The object of the present invention is to make it easier to detect faults in tests using circuit dividing means than before, by making it possible to select the application of the system clock in units of kLsI in the partial logic operation inserted between scan-in and scan-out in the test mode. The system clock operation to other LSIs other than the target LSI k, which is the target of data output, is suppressed, and the partial logic operation using the system clock is limited to all the target LSIs, and the data input to the target LSI is fixed, and the data input to the target LSI is controlled by the data input. The present invention aims to provide a testing method for integrated circuit units that can improve the efficiency of fault detection by providing a means for completely eliminating the effects of racing and the like.

(ei Constituent Axis of the Invention - Dedicated Development and Integration - This purpose is to develop a mounting unit in which a plurality of integrated circuit elements are mounted and connected to form a higher-level logic circuit block. , the integrated circuit elements in the mounting unit are each equipped with a scan-in/out function, and the unit is equipped with means for selecting all integrated circuit elements according to the element address signal and controlling the application of a system clock signal to all the selected integrated circuit elements according to the element address signal. When the unit is in logic mode, the system clock is applied to all the mounted elements to execute logic operations, and in test mode, element address signals are applied to the selection means in partial logic operations inserted between data scan-in and scan-out operations. The system clock is applied only to the selected element, and the logic data sent from the non-selected element to the selected element is fixed, and the scan-out data is sent out one by one for each selected element. This can be achieved by providing a complete test method for integrated circuit element mounting units using circuit dividing means.

(f) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings.

1 is PT plate, 2 a, b- to -n-2+ n-1
, n is LS1.3a, b is decoder, ANDaa-an
y ANDba to bn are AND circuits, NANDa=n is a NAND circuit, and OR is an OR circuit. In the configuration shown in the figure, decoder 3b, AND aa-an J3 and NA
ND a "n' (The configuration except for this is common to conventional logic blocks using PT boards. In the normal logic mode, 0 is applied to the test mode signal terminal TM, and the outputs of NANDa to n are all J. A because
Enable NDaa~an and set system clock CLK
is supplied to all LSI2a-n, processes the data inputted to the data input terminals PIa-r in synchronization with the system clock, and outputs the data to the data output terminal POa=P.
Output data from Os. Also, normal scan-in/
At the output, the data input from PIa=r and the scan address input from scan address terminals 5ADa to IK are received, and a selection signal output from the decoder 3a causes a flip-flip circuit (not shown) in LSI 2 a=n. FF) 'fr Selected and input through data scan terminal Sir Scan and expect FF states in multiple LSIs All decoders 3a
AND b a =b enabled by the selection signal of
Conventional scan-in/out intercropping, which scans in through OR from within nO, can be similarly performed. However, in the present invention, in the state of TM'el, the chip address signal terminal C
NAN obtained by NANDing the selection signal output by the decoder 3b according to the chip address signal from ADa=j
Among Da=n, for example, only NANDn outputs 1, and the other NANDs a to n-1 output OL-, so ANDa
All CLKs applied to a to an-1 are LSI 2
LS that is suppressed by input to a to n-1 and is subject to diagnosis
For example, in the pre-stage LSI of the circuit division surrounded by the diagonal line frame, which is involved in the output at I2n, in the partial logic operation inserted between the system cloud, LSI 2b in the circuit division test means.

The data output from 2k is in a fixed state and is transferred from the previous stage to the LSI.
The racing cause associated with the data input to 2n is removed, and since only LSI 2n executes logical operations associated with the system clock, the output data from LSI 2n is obtained from POr-s and SO, respectively, and the fault detection range is also limited. Therefore, a test method using circuit dividing means that can perform an efficient scan-in-out operation can be obtained. Although the circuit division 1LsI 2nk standard has been described here, it goes without saying that the same test method using the circuit division means for data output and scan-out can be realized for other circuit division means each using the other LSIk as the standard.

Although not shown in the drawings, it is assumed that P I a-r + each LSI 2 a-n and 203 to 205 are connected directly or via an assembly circuit according to the circuit design.

For convenience of explanation, the unit for circuit division and system clock suppression/application selection is set to 11 gLs, but depending on the circuit scale, this unit is divided into LSIs.
', It goes without saying that the same thing can be achieved by setting all units of circuit division and system clock suppression/application selection for each divided part, or vice versa, by setting multiple LSIs as a unit 0 (g) As described in detail, according to the present invention, failures can be detected in tests using circuit dividing means compared to conventional methods. To make it easier, the system clock in test mode which limits the partial logic operations inserted between scan-in/out in test mode = k
It is possible to provide a test method for LSI [mounted units] that is light in burden and has a means for selecting each LSI unit, so that it is possible to provide an effective test program and the like.

[Brief explanation of the drawing]

The figure shows a block diagram of an integrated circuit element mounting unit according to a test method according to an embodiment of the present invention. In the figure, 1 is a printed wiring machine (P is a board) + 2a-H are circuit elements (LSI), and 3a and b are decoders.

Claims (1)

[Claims] In a mounting unit in which a plurality of integrated circuit elements are mounted and connected to form the entire upper logic circuit block, each of the integrated circuit elements in the mounting unit has a scan-in/out function, and The unit is equipped with a means for selecting all integrated circuit elements according to the element address signal and selectively controlling the application of a system clock signal in accordance with the selection. When the mounted unit is in logic mode, the system clock is applied to all mounted elements to generate logic operation sound. At the same time, in the test mode, in the partial logic operation inserted between the data scan-in and scan-out operations, an element address signal is applied to the selection means to apply the system clock only to the selected element, and the application of the system clock is suppressed. A test method for an integrated circuit element mounting unit using a circuit dividing means, characterized in that a transmission logic data 'k1g1' is fixed from an unselected element to a selected element, and scan-out data is transmitted one by one for each selected element.