JPS6096027A - Complementary inverter - Google Patents

Abstract

PURPOSE:To decrease the number of elements and to attain ease of design by constituting a tri-state output complementary MOS inverter where the output is set to a high impedance state by using a transfer gate. CONSTITUTION:A P-channel TRP41 and an N-channel TRN41 constitute the complementary inverter and these gates are connected to P44, N44 of transfer gate constitution. The input to an input terminal I is transferred to a gate of the TRP41 by TRP43 and N43 of transfer gate constitution. An input signal to an output control terminal E becomes a control signal E and an inverted control signal E' via the inverter comprising the TRP45 and N45 and are fed to each transfer gate and the gate comprising the TRP42 and N42. Through the constitution above, the state of the signal I, the control signals E, E', an output signal Y and the TRP41, N41 is listed on the table.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a one-complementary MO8 inverter, particularly a tri-state output complementary MOS inverter that can have nine outputs in high impedance states.

FIG. 1 is a logic diagram of a conventional tri-state output complementary MOS inverter, 2β<Irr is an equivalent circuit of FIG. 1, and FIG. 3 is a truth table. In the figure, from PI to P
71QP channel MOB field effect transistor, Nl
From N7HN channel M (tub with JS field effect transistor.

When an "L" level input voltage is applied to the output control terminal E, the inverted output of the input terminal 1 is output to the output terminal Y'/
c is obtained and functions as an inverter.

- 10,000, when a377 control terminal Etc “H” level voltage is applied, 9a% P channel transistor P
The gate voltage of Nl becomes H# level, the gate voltage of N channel transistor Nl becomes L level, transistors PL and P2 are both turned off, and the output Yrc becomes a high impedance state regardless of the input terminal 1rc. .

Tri-state output complementary gMo with this VC configuration
Since the number of V elements in the S inverter is larger than in a normal inverter, the transmission delay time from input to output becomes longer. In addition, since the gate power a to the complementary transistors PL and Nl of the output Y passes through separate paths r, the transistor occupation area l is both in an on state in a transient state. Please be careful when designing the circuit. It takes 7
'c.

(Object of the Invention) The object of the present invention is to eliminate these drawbacks and to create a trice art output complementary fJM which is easy to design and has fewer problems than the conventional one.
By giving U8 invert 1) /) 0 (Structure of the invention) If the present invention is constructed, the electric field for the output of the 4-basket type and the 14-basket type machine with the power supply end ten minutes and nine straight feet effect transistor,
Connection between the gates of both transistors including O1 and 1
At least 10,000 field effect transistors, control field effect transistors of bar conduction type, and output field effect transistors are connected between the transfer gate of each field effect transistor, the gate of each field effect transistor, and the power supply terminal. A signal input means for applying an input signal to the gate, a signal output means for taking out an output signal from the connection between the output field effect transistors, and a control signal application for applying a control signal to the J-transfer gate and the control field effect transistor. EXAMPLES The present invention will be described in more detail below with reference to the drawings.

FIG. 4 is a circuit diagram showing one embodiment of the present invention.

P-channel transistor P, 11 and N-channel transistor N411'ff complementary inverter overall structure, gates of transistors P41 and N41, σ transfer gate configuration P44. N44 is trying to connect. Transistor 1-'41 gate 2, transistor P42? to the power supply through the gate rz of transistor N41, transistor N42? It is connected to the ground side of the power supply via. The input to the input terminal C is transmitted to the gate of the transistor P41 having a transfer gate configuration. Is the input signal to the output control terminal E an inverter between transistors P45 and N45? The control signal E and the inverted control signal E are applied to each gate of the transfer gate and to the gates of transistors P42 and N42.

When the human power at the output control terminal E is at “L” level,
Transistor P42. N42 [o-transistor P43. When the transfer gate a by N43 and P44 IIc is on, the input a1 to the input terminal S1 is transmitted to the gate of the output transistor P41°N41, and the output terminal Yμ input terminal becomes an inverted output.6° Output control When the terminal E input is at “H” level,
Transistor P43. N43 and P44゜N441C
Both gates of J6 and P42 are turned off, and transistors P42. N42tff turns on
Gate l'ff of transistor P41 "'H" level,
Since the gate rs of the transistor N41 is at "L" level, the output transistor P41. Both terminals N41 are turned off, and the output Y is placed in a high impedance state regardless of the input terminal l. This input signal, control signal, output signal, transistor P41. Figure 5 shows the state of N41 in a tri-state output complementary inverter configured with 60 or more transfer gates. All the same functions can be achieved with ITANO 9 and 1O Sakuko, and it is a circuit! II! 55
The simplification of t can be measured. Furthermore, if used in integrated circuits, a reduction in chip area can be expected.

Since the number of elements entering the path from the input terminal P41 to the output terminal Y is reduced from the conventional three stages to two stages, the transmission delay time is also shortened to about V3.0 Also, the output transistor P41. N41
Kate is Transfer Goo 1P44. Since the common foot of N44vc is fixed, the output transistor P41
．． N41's IiJ operation timing is similar to a normal complementary inverter, and transiently transistor fP41. N41
In the above embodiment, the transfer gate P43 has the advantage that the time during which both are on is minimized.
．． Although N43 is connected to the gate rc of the output transistor P41, the same effect can be obtained by connecting the gate rcH of the output transistor N41.

[Brief explanation of the drawing]

fi1 Figure 1 Logical structure α diagram of a complementary tri-state output MUS inverter, Figure 2 a, etc. circuit in Figure 1, Figure 3
Figure 4 shows the truth table for the circuits in Figures 1 and 2.
FIG. 5 is a circuit diagram showing an embodiment according to the present invention, and FIG. 5 is a truth table for fully explaining the operation of the embodiment. 1, 4... MUR logic circuit, 2, 3... Inverter, N l - N L O, N 41 - N 45 = N
fya 74kMus transistor, Pi~PLO, P41
~P45... P channel MOS transistor, V... power supply (+ side), G... power supply (- side), ■.
...Input terminal, E, E...Output control signal, Y...Output terminal, H...High level signal, L
...Low level signal, Z...High impedance state 85 diagram procedural amendment (method) 1. Indication of incident 1982 Patent Application No. 203985
No. 2, Title of the invention: Complementary inverter 3, Relationship with the person making the amendment: Applicant: 5-33-1-4, Shiba 5-chome, Minato-ku, Tokyo, Agent: 37 J'-5, Shiba 5-chome, Minato-ku, Tokyo, 108 Japan No. 8 Sumitomo Sanda Building NEC Corporation (6591) Patent Attorney Susumu Hara Telephone Tokyo (03) 456-3111 (Main Representative) (Contact information L1 Hondenki Co., Ltd. Office Department N5, Date of amendment order
January 31, 1980 (Delivery 8.) 6. Original contents of the specification and drawings to be amended 2. - Paper tray 8. Attached documents (full text correction) specification and (corrected) drawings 1 copy each Details Document 1, Title of the Invention Complementary Inverter 2, Claims P-channel type and N-channel type output transistors connected in series with each other, and a first transfer gate connected between the gate electrodes of these output transistors. ,
A P-channel control transistor connected between the gate of the P-channel transistor among the output transistors and the power supply (+ side), and the gate of the N-channel transistor among the output transistors and the power supply (-side)
A complementary inverter comprising: an N-channel transistor connected therebetween; and a second transformer 7 agate that controls application of an input signal to the gate of the output transistor. 3. Detailed Description of the Invention (Technical Field of the Invention) The present invention relates to a complementary MOS inverter, particularly a tri-state output complementary MOS inverter whose output can be set to a high impedance state. A logical connection diagram of an OS inverter, FIG. is the equivalent circuit of FIG. In the figure, Pl to Pl are P-channel inter-channel O8 field effect transistors, and N1 to N7 are N-channel MO8 field effect transistors. When an "L" level input voltage is applied to the output control terminal E, an inverted output of the input terminal (2) is obtained at the output terminal Y, and the circuit functions as an inverter. On the other hand, when a high level voltage is applied to the output control terminal E, the gate voltage of the P channel transistor P1 is high, and the gate voltage of the N channel transistor N is
When the gate voltage of 1 is at II L'' level, both transistors pP1 and P2 are off, and the output Y is in a high impedance state regardless of the input terminal 2. The above operation is shown in Table 1. In Diagram 1, Z# indicates a high impedance state.Table 1 Complementary MOS with tri-state output configured in this way
Since an inverter has more element classes than a normal inverter, it has the drawbacks that the propagation delay time from input to output increases and the area occupied by the entire transistor increases.゛Also, the complementary transistor P of the output Y
Since the gate inputs to I and Nl are routed through separate paths, both transistors PI and Nl may be turned on in a transient state, which requires care in circuit design. (Object of the Invention) An object of the present invention is to eliminate these drawbacks and to provide a tri-state output complementary type MO which is easy to design with a smaller number of elements than the conventional one.
It is to provide an S inverter. (Structure of the Invention) According to the present invention, output field effect transistors of one conductivity type and another conductivity type are connected directly between power supply terminals, and a first transfer transistor is connected between the gates of these transistors. a control field effect transistor of the same conductivity type as each field effect transistor connected between the gate and the power supply terminal of each field effect transistor;
Signal input means for applying an input signal to at least one gate of the output field effect transistor, signal output means for taking out the output signal from a connection between the output field effect transistors, the transfer gate and the control field effect transistor. A complementary inverter having a control signal applying means for giving a control signal to the inverter is obtained. (Example) Hereinafter, the present invention φJ will be explained in detail with reference to the drawings. FIG. 3 is a circuit diagram showing an embodiment according to the present invention, in which a P-channel transistor P41 and an N-channel transistor N41 constitute a complementary inverter, and a transistor P4]
and N41 gate is P44 of transfer gate configuration.
．． N44 is connected. The gate of the transistor P41 is connected to the power supply via the transistor P42, and the gate of the transistor N41 is connected to the ground side of the power supply via the transistor N42. The input to the input terminal Che is transmitted to the gate of transistor P41 by transistors P43 and N43 in a transfer gate configuration. The input signal to the output control terminal E is the transistor P45.
and N45, each gate of the transfer gate and the transistor P42. ! : Applied to the gate of N42. When the input to the output control terminal E is at L'' level, the transistors P42 and N42 are in the off state.The transfer gate formed by the transistors P43 and N43 and P44'N44 is in the on state and the input to the input terminal is as follows.
is transmitted to the gate of output transistor P41°N41,
Output terminal Y is connected to the inverted output of input terminal I. Output control output (when the input of child E is I(" level), transistors P43, N43 and P44゜N44
Both transfer gates are in the off state.
Transistor P42. N42 is turned on. Since the gate of the transistor P41 is at the ``H'' level and the gate of the transistor N41 is at the ``L'' level, both the output transistors P41 and N41 are in the off state, and the output Y has a high impedance regardless of the input terminal ■. Table 2 shows the input signal, control signal, output signal, and the states of transistors P41 and N41. In No. 2, the conventional type shown in Figure 1 requires 14 transistor elements, but the same function can be achieved with 10 elements, simplifying the circuit configuration.If used in a large integrated circuit, the chip area can be reduced. Since the number of elements entering the #I path from the input terminal I to the output terminal Y is reduced from the conventional three stages to two stages, the transmission J31 delay time is also shortened to about 2/3. Output transistor P4
1. The gate of N41 is the transfer gate P44. N
44, the output transistors P41. The operation timing of transistor P41 is the same as that of a normal complementary inverter. N4
This has the advantage that the time that both 1 and 1 are on can be minimized. In the above embodiment, transfer gate P43.
Although N43 is connected to the gate of the output transistor P41, young fruits of the same type can be found even if N43 is connected to the gate of the output transistor N41. 4. Brief explanation of the drawings Fig. 1 is a logical configuration diagram of a conventional tra/f-state output complementary MOS inverter, Fig. 2 is an equivalent circuit of Fig. 1, and Fig. 3 is an equivalent circuit diagram of Fig. 1.
The figure is a circuit diagram showing an embodiment according to the present invention. 1.4...MOR logic circuit, 2,3...
・Inverter, N1~NIO, N41~N, 15...
...N channel MO8) transistor, PI-PIO
, P41 to P45...P channel MO3) synristor, ■...Power supply (+ side), G...
・Power supply (-8III>, X... input terminal, E・
...Output control signal, Y...Output terminal. E q 转 l flash

Claims (1)

[Claims] P-channel type and PE-channel type output transistors connected in series/C to each other, a first transformer connected between the gate electrodes of these output transistors, and P of the output transistors. A P-channel type control transistor connected between the gate of the channel type transistor and the power supply (+ side), and a continuous connection between the gate of the N-channel transistor inside the output transistor and the power supply (- side). A complementary inverter, characterized in that the complementary inverter has a second transfer gate that controls the application of an input signal to the gate of the output transistor.