JPS6097619A - Manufacture of semiconductor - Google Patents

Manufacture of semiconductor

Info

Publication number
JPS6097619A
JPS6097619A JP58204795A JP20479583A JPS6097619A JP S6097619 A JPS6097619 A JP S6097619A JP 58204795 A JP58204795 A JP 58204795A JP 20479583 A JP20479583 A JP 20479583A JP S6097619 A JPS6097619 A JP S6097619A
Authority
JP
Japan
Prior art keywords
oxygen concentration
silicon
crystal
thermal stress
apt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58204795A
Other languages
Japanese (ja)
Inventor
Hirobumi Shimizu
博文 清水
Masato Fujita
正人 藤田
Kazunari Kobayashi
一成 小林
Akira Yoshinaka
吉中 明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58204795A priority Critical patent/JPS6097619A/en
Publication of JPS6097619A publication Critical patent/JPS6097619A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Abstract

PURPOSE:To prevent a minute defect and the generation of warping and contrive to improve yield by determining the inter-lattice oxygen concentration included in a silicon crystal at a specific value. CONSTITUTION:By determining the inter-lattice oxygen concentration in a silicon crystal at 4.5X10<17>-12.0X10<17>atom/cm<3>, a silicon wafer which is difficult in generating a minute defect or a warp by thermal stress can be obtained, while the process can be stabilized and the yield can be improved. If the inter- lattice oxygen concentration in a silicon crystal is less than 4.5X10<17>atom/cm<3>, the crystal is too clean and a surface lamination defect is apt to be generated due to the effect of contamination by a very small amount of metal ion impurity. On the other hand, if the interstitial oxygen concentration is more than 12.0X10<17>atom/cm<3>, a minute defect is apt to be formed during heat treatment and a positioning due to thermal stress is apt to be generated.

Description

【発明の詳細な説明】 [技術分野] 本発明は半導体製造技術、特に、シリコン(Si)より
なる半導体ウェハを製造するのに適用して効果のある半
導体製造技術に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor manufacturing technology, and particularly to a semiconductor manufacturing technology that is effective when applied to manufacturing semiconductor wafers made of silicon (Si).

[背景技術] 現在使用されている半導体デバイスの主流材料はシリコ
ン結晶であり、その育成法としてはチョクラルスキー法
(CZ法、引上法)とフローティングゾーン法(FZ法
、帯溶融精製法)がある。
[Background technology] The mainstream material of semiconductor devices currently used is silicon crystal, and the methods for growing it are the Czochralski method (CZ method, pulling method) and the floating zone method (FZ method, zone melting refining method). There is.

現在LSIを中心とするシリコンデバイスに使う大部分
のウェハはC2法によって育成している。
Currently, most wafers used for silicon devices, mainly LSIs, are grown using the C2 method.

C2法によるC2結晶は石英るつぼ内でシリコンを溶融
して引き上げるため、るつぼから溶出する酸素原子が単
結晶中に偏析し、通常の育成技術では〜15 X 10
’atoa+s /dの格子間酸素を含有するのが普通
となっている。
Since C2 crystals produced by the C2 method are pulled by melting silicon in a quartz crucible, oxygen atoms eluted from the crucible segregate in the single crystal, and with normal growth techniques ~15 x 10
'atoa+s/d of interstitial oxygen is common.

一方、FZ法(帯溶融精製法)によるFZシリコンウェ
ハは、格子間酸素濃度はCZウェハに比して約2桁低い
が(〜10 I6atoms /cd) 、デバイスプ
ロセスでの熱応力によってスリップやそりが発生し易い
ため、現在では高抵抗を必要とするサイリスク素子等の
限られた用途があるのみである。
On the other hand, FZ silicon wafers manufactured using the FZ method (zonal fusion refining method) have an interstitial oxygen concentration that is approximately two orders of magnitude lower than that of CZ wafers (~10 I6atoms/cd), but are susceptible to slipping and warping due to thermal stress during the device process. Because of the tendency for this to occur, it currently has only limited uses, such as in cyrisk elements that require high resistance.

ところで、結晶中の酸素濃度がデバイスプロセスの熱処
理温度で固溶限以上になる場合、過飽和酸素の析出が起
こる。析出のし易さは結晶育成中あるいは成長後の炉内
熱履歴によって生ずる微小欠陥の核の密度と、酸素濃度
に依存する。酸素析出物は転位ループや積層欠陥等の微
小欠陥を誘発する。
By the way, when the oxygen concentration in the crystal exceeds the solid solubility limit at the heat treatment temperature of the device process, precipitation of supersaturated oxygen occurs. The ease of precipitation depends on the density of microdefect nuclei generated by the thermal history in the furnace during or after crystal growth, and on the oxygen concentration. Oxygen precipitates induce micro defects such as dislocation loops and stacking faults.

このような微小欠陥は、熱応力転位の発生を促進するの
で、欠陥密度が高いウェハ程、そり変形し易い。そりが
大きいと、フォトリソグラフィ工程でのマスクのパター
ンの転写精度が低下する。
Since such minute defects promote the occurrence of thermal stress dislocations, a wafer with a higher defect density is more likely to warp. If the warpage is large, the accuracy of transferring the mask pattern in the photolithography process will be reduced.

一方、導入された熱応力転位はデバイスの特性を劣化さ
せ、歩留り低下の原因となっている。固体撮像素子では
結晶欠陥の存在が画像に白点不良をもたらすので、結晶
欠陥の発生し難い結晶に対する要求が強い。
On the other hand, the introduced thermal stress dislocations deteriorate device characteristics and cause a decrease in yield. In solid-state imaging devices, the presence of crystal defects causes white spot defects in images, so there is a strong demand for crystals that are less likely to have crystal defects.

また、イントリンシック・ゲッタリングを行い素子歩留
りの向上を図る試みが行われているが、これに適する結
晶としては、格子間酸素の濃度が〜15 X 10”a
toms /cta程度含程度子いる−ことが望ましい
とされている。
In addition, attempts have been made to improve device yield by performing intrinsic gettering, but a crystal suitable for this purpose has an interstitial oxygen concentration of ~15 x 10"a
It is said that it is desirable to have a particle size of about toms/cta.

[発明の目的] 本発明の目的は、微小欠陥が発生しにくく、また熱応力
でそりが発生しにくく、歩留りを向上させることのでき
る半導体製造技術を提供することにある。
[Object of the Invention] An object of the present invention is to provide a semiconductor manufacturing technology that is less likely to generate minute defects, less likely to warp due to thermal stress, and capable of improving yield.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[発明の概要] 本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。
[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

すなわち、シリコンよりなる半導体におけるシリコン結
晶中に含まれる格子間酸素濃度が4.5×10” 〜1
2.OX 10’atoms /ctlとなるようにす
ることにより、微小欠陥やそりの発生しにくい半導体を
製造することができ、歩留りの向上を実現することがで
きる。
That is, in a semiconductor made of silicon, the interstitial oxygen concentration contained in the silicon crystal is 4.5 × 10" ~ 1
2. By setting OX 10'atoms/ctl, it is possible to manufacture a semiconductor in which micro defects and warpage are less likely to occur, and it is possible to improve the yield.

[実施例1] 一般に、育成中(as−groeyn)のウェハの格子
間酸素濃度と、それを熱処理して発生する微小欠陥密度
の間には密接な関係がある。
[Example 1] Generally, there is a close relationship between the interstitial oxygen concentration of a wafer during growth (as-groeyn) and the microdefect density generated by heat treating the wafer.

そこで、本発明者らは一例として、異なる酸素濃度を含
有する単結晶を育成し、それから作製したウェハの熱応
力によるそりを調べ、そりが起こりにくいウェハに含ま
れる格子間酸素濃度の範囲を見い出すべり鋭意実験研究
を行った。
Therefore, as an example, the present inventors grew single crystals containing different oxygen concentrations, examined the warping caused by thermal stress in the wafers produced from the single crystals, and found a range of interstitial oxygen concentrations contained in the wafers in which warping is less likely to occur. We conducted extensive experimental research.

゛この実験用に使用したシリコン単結晶の育成条件は次
の表1に示す通りであった。
゛The growth conditions for the silicon single crystal used for this experiment were as shown in Table 1 below.

これらの単結晶試料■、■、■のウニ八サンプリング位
置はそれぞれ第1図(al、伽)、(C)に示す各単結
晶インゴットについて示されている。
The sampling positions of these single crystal samples (1), (2), and (2) are shown for each single crystal ingot shown in FIGS. 1 (al, 2) and (C), respectively.

そして、第2図に示すような処理条件での強制熱処理(
1)、(I[)によりウェハのそり量を評価した。
Then, forced heat treatment (
1) The amount of warpage of the wafer was evaluated using (I[).

このウェハそり量の評価結果を比較ウェハの評価結果と
共に単結晶インゴット内の位置でプロットしたところ、
第3図および第4図に示すような結果が得られた。第3
図と第4図において、縦軸はそり[μm]、横軸は単結
晶インゴットの肩からの位置[CIl]を表している。
When the evaluation results of this wafer warp amount were plotted along with the evaluation results of comparison wafers at the position within the single crystal ingot,
The results shown in FIGS. 3 and 4 were obtained. Third
In the figure and FIG. 4, the vertical axis represents the warpage [μm], and the horizontal axis represents the position [CIl] from the shoulder of the single crystal ingot.

 −一方、各試料■、■、■における単結晶インゴット
の肩からの位置と微小欠陥密度との関係は第5図に示さ
れる通りであった。
- On the other hand, the relationship between the position from the shoulder of the single-crystal ingot and the microdefect density for each sample (1), (2), and (2) was as shown in FIG.

また、各試料■、■、■における単結晶インゴットの肩
からの位置と酸素濃度との関係は第6図に示される通り
であった。
Furthermore, the relationship between the position from the shoulder of the single crystal ingot and the oxygen concentration in each sample (2), (2), and (2) was as shown in FIG.

第6図の結果によれば、酸素濃度が7.5X1017〜
12 X 10”atoms /cJでは熱応力による
そりが極端に小さくなっている。また、強力な磁場の中
で結晶成長を行うこと等により、酸素濃度が4.5X1
017〜?、5X101フato+*s /cllの範
囲でも良好なそり抑制効果が得られることが本発明者ら
の研究によって判明している。
According to the results in Figure 6, the oxygen concentration is 7.5X1017~
At 12 x 10"atoms/cJ, the warpage due to thermal stress is extremely small. Also, by performing crystal growth in a strong magnetic field, the oxygen concentration is 4.5 x 1
017~? , 5X101 fato+*s/cll, it has been found through research by the present inventors that a good warpage suppressing effect can be obtained.

なお、この格子間酸素濃度の換算値は米国標準規格(A
STM)のF121−79によるものであり、本明細書
の全体を通じてこの換算値が用いられている。
The converted value of this interstitial oxygen concentration is based on the American standard (A
STM) F121-79, and this converted value is used throughout this specification.

このようなウェハそり量は第7図および第8図に示すよ
うに、強制熱処理の如何を問わず、微小欠陥密度に強く
依存する。
As shown in FIGS. 7 and 8, the amount of wafer warpage strongly depends on the microdefect density, regardless of the forced heat treatment.

このように、本実施例によれば、シリコン結晶の格子間
酸素濃度を4.5X10”から12. OX 10 ”
 atoms /cJにすることにより、微小欠陥が生
じに(り、熱応力でそりにくいシリコンウェハを得るこ
とができ、プロセスの安定化を図り、歩留りを向上させ
ることができる。
In this way, according to this example, the interstitial oxygen concentration of the silicon crystal is increased from 4.5X10'' to 12.OX10''.
By using atoms/cJ, it is possible to obtain a silicon wafer that is less likely to warp due to thermal stress due to the generation of minute defects, thereby making it possible to stabilize the process and improve the yield.

シリコン結晶の格子間酸素濃度が4.5X1017at
oms /cI!よりも低いと、結晶がクリーンすぎて
、微量な金属イオン不純物による汚染の影響により表面
積層欠陥が発生し易いという問題が生じてしまう。その
意味では、格子間酸素濃度は好ましくは7.5 X 1
0” 〜12.OX 10”atoms /c+aであ
る。
The interstitial oxygen concentration of silicon crystal is 4.5X1017at
oms/cI! If it is lower than , the problem arises that the crystal is too clean and surface stacking defects are likely to occur due to the influence of contamination by minute amounts of metal ion impurities. In that sense, the interstitial oxygen concentration is preferably 7.5
0" to 12.OX 10"atoms/c+a.

一方、シリコン結晶の格子間酸素濃度が12.0X 1
0 ” atoms / cLaよりも高くなると、熱
処理中に微小欠陥が形成され易くなり、熱応力転位が発
生し易くなるという問題が生じる。
On the other hand, the interstitial oxygen concentration of silicon crystal is 12.0X 1
When the value is higher than 0'' atoms/cLa, a problem arises in that micro defects are more likely to be formed during heat treatment and thermal stress dislocations are more likely to occur.

[効果] (■)、シリコン結晶の格子間酸素濃度を4.5X10
” 〜12. OX 10 ” atoms /cdに
することにより、酸化拡散プロセス等で微小欠陥が発生
しにくく、また熱応力によるスリップやそりの発生しに
くいシリコン半導体が得られ、歩留りを向上させること
ができる。
[Effect] (■), the interstitial oxygen concentration of silicon crystal is 4.5X10
"~12. OX 10" atoms/cd makes it possible to obtain a silicon semiconductor that is less likely to generate minute defects in the oxidation diffusion process, etc., and less prone to slip or warp due to thermal stress, thereby improving the yield. can.

(2)、格子間酸素濃度を7.5XI01フ〜l 2.
 OX 10 ” atoms /−にすれば、微量な
金属イオン不純物による汚染に起因する表面積層欠陥が
より発生しにく(、より良好なシリコン半導体が得られ
る。
(2), the interstitial oxygen concentration is 7.5XI01f~l 2.
If OX 10 '' atoms/- is used, surface stacking defects due to contamination by trace amounts of metal ion impurities are less likely to occur (and a better silicon semiconductor can be obtained).

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。
Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof. Nor.

たとえば、ウェハの熱処理条件等は前記以外のものを選
ぶことができる。
For example, wafer heat treatment conditions etc. may be selected from conditions other than those described above.

特に、本発明による半導体製造方法を固体撮像素子用に
使用すれば、白点不良率が低(、プローグ検査歩留りも
大巾に向上させることができる。
In particular, if the semiconductor manufacturing method according to the present invention is used for solid-state imaging devices, the white spot defect rate can be reduced (and the prologue test yield can also be greatly improved).

また、特に、デバイスが高集積化される程ウェハのそり
のフォトリソグラフィ工程での転写精度に及ぼす影響は
大きく、また、接合サイズも小さくなり′、微小な結晶
欠陥の特性に及ぼす影響は大となるので、本発明は高集
積化デバイスや固体撮像素子に適用すれば、最も大きい
効果が得られる。
In particular, as devices become more highly integrated, wafer warpage has a greater effect on transfer accuracy in the photolithography process, and as the bond size becomes smaller, the effect of microcrystal defects on the characteristics becomes greater. Therefore, the greatest effect can be obtained if the present invention is applied to highly integrated devices or solid-state image sensors.

[利用分野] 以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である高集積化デバイスや
固体撮像素子に適用した場合について説明したが、それ
に限定されるものではなく、たとえば、他の様々なMO
S型あるいはバイポーラ型素子に適用でき、素子の高集
積化が進めば進む程有用である。また、本発明はサイリ
スク等にも適用できる。
[Field of Application] In the above explanation, the invention made by the present inventor is mainly applied to highly integrated devices and solid-state image sensors, which are the background fields of application, but the present invention is not limited thereto. , for example, various other MOs
It can be applied to S type or bipolar type devices, and becomes more useful as devices become more highly integrated. Further, the present invention can be applied to Cyrisk and the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(al、(b)、(C)は各種単結晶試料におけ
るシリコンウェハのテンプリング位置を示す図、第2図
はシリコンウェハ試料に対する熱処理条件とそのそり評
価法を示す図、 第3図は熱処理によるそり量を示す図、第4図は他の条
件での熱処理によるそり量を示す図、 第5図は単結晶インゴットの各種位置における微小欠陥
密度を示す図、 第6図は同じく酸素濃度を示す図、 第7図は微小欠陥密度とそり量の関係を示す図、第8図
は他の熱処理条件における微小欠陥密度とそり量の関係
を示す図である。 第 5 図 岸−*韻Ij′二γ卜つ4イ11かうの4立“;11□
(Q肌)第6図
Figures 1 (al, (b), and (C) are diagrams showing the tempering positions of silicon wafers in various single crystal samples, Figure 2 is a diagram showing heat treatment conditions for silicon wafer samples and their warpage evaluation method, and Figure 3 Figure 4 shows the amount of warpage due to heat treatment, Figure 4 shows the amount of warpage due to heat treatment under other conditions, Figure 5 shows the micro defect density at various positions of the single crystal ingot, Figure 6 is the same. FIG. 7 is a diagram showing the relationship between the micro defect density and the amount of warpage. FIG. 8 is a diagram showing the relationship between the micro defect density and the amount of warpage under other heat treatment conditions. *Rhyme Ij′2γ卜ツ4i11かの四stand”;11□
(Q skin) Figure 6

Claims (1)

【特許請求の範囲】 1、シリコンよりなる半導体の製造方法において、シリ
コン結晶中に含まれる格子間酸素濃度を4.5X 10
” 〜12.OX 10”atoms /adとするこ
とを特徴とする半導体製造方法。 2、格子間酸素濃度が7.5X10”〜12. OX 
10 ” atoIIls / cjであることを特徴
とする特許請求の範囲第1項記載の半導体製造方法。
[Claims] 1. In a method for manufacturing a semiconductor made of silicon, the interstitial oxygen concentration contained in the silicon crystal is set to 4.5×10
” ~12.OX 10”atoms/ad. 2. Interstitial oxygen concentration is 7.5X10"~12.OX
10'' atoIIls/cj. The semiconductor manufacturing method according to claim 1.
JP58204795A 1983-11-02 1983-11-02 Manufacture of semiconductor Pending JPS6097619A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58204795A JPS6097619A (en) 1983-11-02 1983-11-02 Manufacture of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58204795A JPS6097619A (en) 1983-11-02 1983-11-02 Manufacture of semiconductor

Publications (1)

Publication Number Publication Date
JPS6097619A true JPS6097619A (en) 1985-05-31

Family

ID=16496480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58204795A Pending JPS6097619A (en) 1983-11-02 1983-11-02 Manufacture of semiconductor

Country Status (1)

Country Link
JP (1) JPS6097619A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62202900A (en) * 1986-03-03 1987-09-07 Toshiba Corp Semiconductor silicon wafer and production thereof
JPH0437027A (en) * 1990-06-01 1992-02-07 Toshiba Ceramics Co Ltd Wafer retaining boat
WO1994016124A1 (en) * 1993-01-06 1994-07-21 Nippon Steel Corporation Method and apparatus for predicting crystal quality of single-crystal semiconductor
GB2279586A (en) * 1993-01-06 1995-01-11 Nippon Steel Corp Method and apparatus for predicting crystal quality of single-crystal semiconductor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62202900A (en) * 1986-03-03 1987-09-07 Toshiba Corp Semiconductor silicon wafer and production thereof
JPH0437027A (en) * 1990-06-01 1992-02-07 Toshiba Ceramics Co Ltd Wafer retaining boat
WO1994016124A1 (en) * 1993-01-06 1994-07-21 Nippon Steel Corporation Method and apparatus for predicting crystal quality of single-crystal semiconductor
GB2279586A (en) * 1993-01-06 1995-01-11 Nippon Steel Corp Method and apparatus for predicting crystal quality of single-crystal semiconductor
US5485803A (en) * 1993-01-06 1996-01-23 Nippon Steel Corporation Method of predicting crystal quality of semiconductor single crystal and apparatus thereof

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