JPS609934Y2 - Recording/playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording and reproducing apparatus that performs recording and reproducing using a recording and reproducing head.

In a recording/reproducing apparatus equipped with one recording/reproducing head, a relay or a slide switch is generally used to selectively connect a recording circuit and a reproducing circuit to this head.

However, it is preferable to use an electronic switch for such a switching circuit in terms of manufacturing cost, reliability, etc.

Figure 1 shows the recording/recording of a conventionally known tape recorder.
This is a regeneration circuit.

During recording, a high level switching signal a is supplied to the terminal 8 in FIG. 1 via the resistor R2 to the transistor T3.
The transistor T3 is turned on and one end of the recording/reproducing head 7 is grounded.

Further, an inverted signal a of the switching signal a is supplied to the terminal 6, and the transistors TI and T2 are turned off.

Therefore, the recording audio signal supplied to the terminal 1 is supplied to the recording/reproducing head 7 through the recording amplifier 2 including the equalizer 3 and the bias trap circuit formed from the capacitor C1, the coil L1, and the capacitor C2.

At this time, an AC bias signal C is supplied to the head 7 from the terminal 11 via the variable capacitor 5.

Therefore, during recording, the on-state transistor T3 is inserted in series with the recording/reproducing head 7, so that as the recording signal increases, distortion increases and the linearity of recording characteristics deteriorates.

Furthermore, during playback, the switching signal a becomes low level, turning off the transistor T3, and its inverted signal a (high level) is supplied to the transistors TI and T2 via the resistor R1 and the diodes D1 and D2, respectively. , transistors TI and T2 are turned on.

Therefore, one end of the recording/reproducing head 7 is grounded, and a reproduced audio signal d obtained from the other end is supplied to a reproduction amplifier 9 including an equalizer 10.

For this reason, since transistors TI and T2 in an on state are inserted in series with the recording/reproducing head 7, the S/N of the reproduced signal d deteriorates.

In particular, thermal noise from the transistors T1 and T2 is likely to be mixed into the reproduced signal.

Note that the transistors TI and T2 are connected in cascade in consideration of the withstand voltage for the AC bias signal C when they are off.

As described above, the conventional recording/reproducing switching circuit using stocking transistors shown in FIG. 1 causes large distortion during recording, and tends to have an adverse effect on the S/H of the reproduced signal.

The present invention has been devised in view of the above-mentioned problems, and allows recording and reproduction states to be switched without using switching transistors.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a recording/reproducing circuit of a tape recorder showing an embodiment of the present invention.

In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals.

In FIG. 2, the recording amplifier 2 is constituted by a complementary pEPP (single-ended bush-pull) circuit which is derived from a PNP transistor T4 and an NPN transistor T5.

These transistors T4. T5 has resistors R7 and R8 on its emitter, and also has a capacitor C6 and a coil L2.
Equalizer circuit, capacitor C7, coil L
Each of the devices is equipped with an equalizer circuit consisting of three equalizer circuits.

During recording, a DC power of, for example, 12 V is supplied from the terminal 14 to the recording amplifier 2, and the amplifier becomes operational.

The recorded audio signal is transmitted from terminal 1 to transistor T4 via resistor R3 and coupling capacitors C3 and C4, respectively.
．． Supplied to the base of T5.

Note that the resistors R4, R5, and R6 are bias resistors.

The output of the 5EPP circuit is the coupling capacitor C1,
an equalizer circuit consisting of a resistor R9 and a capacitor C5;
The signal is supplied to the recording/reproducing head 7 through a bias trap circuit consisting of a branch point A1 with the reproduction system, a capacitor C2, and a coil L1.

Also, the bias signal C is supplied from the terminal 11 to the head 7 via the level adjustment variable capacitor C5, as in the conventional case.

Note that during recording, the recording signal is also supplied to the reproduction system from the branch point A, but the power supplied to the reproduction amplifier 9 from the terminal 16 is turned off, so that the reproduction amplifier 9 does not operate.

Note that the configuration may be such that the output of the reproduction amplifier 9 is muted during recording.

In addition, at the front stage of the reproduction system, there is a transistor T6, a resistor RIG,
Since the emitter follower circuit 15 with high input impedance consisting of R11 and R12 is inserted, the recording current leaking from the branch point A to the reproduction system is very small.

Therefore, the linearity of recording characteristics does not deteriorate.

Note that this emitter follower circuit 15 may be a source follower circuit using an FET.

During reproduction, power is supplied from the terminal 16 to the reproduction amplifier 9, and the reproduction amplifier 9 becomes operational.

The reproduced audio signal obtained from the recording/reproducing head 7 is transmitted through a bias trap circuit, a branch point A1, a coupling capacitor C8
The signal is supplied to the transistor T6 of the emitter follower circuit 15 through the transistor T6.

The output signal of the transistor T6 is supplied to the reproducing amplifier 9 via the resistor R13.

Further, during reproduction, the power supply supplied to the terminal 14 is turned off, and the recording amplifier 2 is configured to be in an inoperable state.

Therefore, the transistor T4 configuring the 5EPP circuit of the recording amplifier 2. Since both T5 are turned off, the impedance of the recording amplifier 2 seen from the branch point A becomes extremely high.

Therefore, during playback, the playback signal leaking from branch point A to the recording system is extremely small, and the S/N of the playback signal is reduced due to the leakage current.
It doesn't seem to get worse.

Note that when the recording amplifier 2 is constructed from a conventional class A amplifier or the like, even if the output transistor is turned off by turning off the power to this amplifier, there is a load resistance of the output transistor. The impedance on the amplifier side is low, and the playback signal leaks to the recording side, resulting in signal S/
This causes the inconvenience that N deteriorates.

In this embodiment, in order to prevent the recording current from leaking to the reproduction system during recording, an emitter follower circuit 15 with high impedance input is provided in the front stage of the reproduction system. N may worsen.

Therefore, the bias resistor RIO of the emitter follower circuit 15
, R11 suppress the collector current of the transistor T6 to, for example, about 100 μA, thereby reducing the influence on the S/N ratio of the reproduced signal.

Note that the recording amplifier 2 is powered on and the playback amplifier 9 is powered off during recording, and the recording amplifier 2 is powered off during playback.
Control of turning off the power and turning on the power of the playback amplifier 9 may be performed using a switch that operates in conjunction with the record button and playback button of the tape recorder.

Alternatively, the above control may be performed by turning on and off an electronic switch based on a control signal from a system control circuit (not shown) of the tape recorder.

Furthermore, as the 5EPP circuit of the recording amplifier 2, a complementary type was used in the embodiment, but an input cadence type, a CE
5EP of minute division length complementary Darlington type
It may also be a P circuit.

As mentioned above, this invention has a 5EP recorder at one end of the recording/playback head.
A recording amplifier having an output stage of P configuration is connected to an emitter follower circuit, and a reproduction amplifier is connected to the output end of the emitter follower circuit, so that the power of the recording amplifier is turned off during reproduction.

Therefore, when the power to the recording amplifier is turned off during playback, the impedance of the 5EPP circuit of the recording amplifier as seen from the head side becomes extremely high, making it impossible to effectively block the reproduction signal from leaking from the head to the recording amplifier side. can.

Therefore, it can be configured to switch between recording and playback without using an electronic switch (switching transistor) inserted in series in a conventional recording/playback head, improving linearity of recording characteristics and playback. Inconveniences such as deterioration of signal S/N ratio due to switching transistors do not occur.

[Brief explanation of the drawing]

Figure 1 shows the recording/recording of a conventionally known tape recorder.
Reproduction System Circuit FIG. 2 shows a recording/reproduction system circuit of a tape recorder showing an embodiment of the present invention. In addition, in the symbols used in the drawings, 2...
・Recording amplifier, 7...Recording/playback head, 9...
...Reproduction amplifier, T4. T5...Transistor.

Claims (1)

[Scope of utility model registration request] A recording amplifier equipped with a 5EPP output stage and an emitter follower circuit are connected to one end of the recording/reproducing head, and a reproduction amplifier is connected to the output end of the emitter follower circuit, and the power of the recording amplifier is turned off during reproduction. A recording/playback device designed to