JPS6110231Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to an electronic timer that allows control over multiple items under precise time management.

Mechanical timers have conventionally been used in various fields, but mechanical timers have problems such as poor control time accuracy and difficulty in setting complex patterns for control equipment.

On the other hand, an electronic timer using an electronic circuit has also been proposed.The basic operating principle of this electronic timer is It is configured to store the time and the operating pattern of the control equipment group in an electrical storage device (hereinafter referred to as memory), and to generate a control pulse when the control time stored in this memory and the time of the clock device match. Based on the operation pattern of the control equipment group stored in the memory mentioned above,
It is configured to control a group of control devices.

Such electronic timers are inevitably more difficult to set than conventional mechanical timers.

In other words, in the case of a mechanical timer, at least the control time can be set while being visually checked, for example, by attaching a pawl to a disc rotated by a motor with time scales, and it is also possible to set the control time while visually checking it. However, the conventional electronic timer described above has the disadvantage that the settings cannot be visually confirmed.

In view of the above points, this invention was devised in order to solve such problems and eliminate such drawbacks.The purpose of this invention is to make all electronic circuits, and to set the control time or the operation pattern of the control equipment group. Another object of the present invention is to provide an electronic timer that can be set while visually checking the same as a mechanical timer, and then visually confirming the set contents again.

Next, an embodiment of the electronic timer of this invention will be explained based on the drawings. Fig. 1 is a block diagram showing one embodiment, and Fig. 2 is a concrete diagram showing the main parts of this invention in detail. FIG. 2 is a circuit diagram showing an example.

First, starting from the case of Fig. 1, reference numeral 1 in the figure indicates the control time from the control time setting digital switch group 1-1 or the operation pattern setting digital switch group 1-2 for setting the operation pattern of the control equipment group. Alternatively, it is a group of digital switches that generate a binary coded decimal code output (hereinafter referred to as BCD code output) for setting a driving pattern.

The settings of the control time setting digital switch group 1-1 and operation pattern setting digital switch group 1-2 of digital switch group 1 are stored in memory 2.
It is beginning to be sent out.

This memory 2 transfers the setting contents of the control time setting digital switch group 1-1 and the operation pattern setting digital switch group 1-2 to the address specified by the contents of the address counter 3 by the mode switch 4 and the write/read switch 5. It stores data at the timing set by the position.

Further, the mode switch 4 is a mode switch having three positions for determining the operating mode of the electronic timer of this invention, a setting operation and a confirmation operation, and is adapted to send signals to selectors 6 and 7.

The selector 6 controls the mode switch 4 to determine whether the input pulse to be sent to the address counter 3 is a pulse generated by the scan oscillator 8 or a pulse generated by operating the 2-position write/read switch 5. It is selected based on the signal.

On the other hand, numeral 9 is a clock pulse generator which generates a reference clock pulse based on the oscillation frequency of the crystal oscillator of the clock pulse generator 9 or the commercial frequency, and sends this clock pulse to the clock section 10.

This clock section 10 consists of a counter circuit for counting clock pulses introduced from a clock pulse generator 9 to obtain time.
1 and the selector 7 mentioned above.

The coincidence circuit 11 compares the contents of the memory 2 at the address specified by the contents of the address counter 3 with the contents of the clock section 10, generates a pulse when the contents of both are the same, and sends this pulse to the memory circuit 12.
It is now being sent to

This memory circuit 12 operates using the pulses generated by the coincidence circuit 11 as a control signal, and stores the operation patterns of the control equipment group stored in the memory 2 in advance in correspondence with control times, and the contents of this memory circuit 12 are as follows. is output through a buffer circuit 13.

Further, the selector 7 is connected to the mode switch 4.
The control signal is used to select whether the content to be displayed on the next stage time display device 14 is the content of the memory 2 or the content of the clock unit 10.

Next, the operation of the electronic timer of this invention constructed as described above will be briefly described.

First, when setting the control time and the operation pattern of the control equipment group corresponding to that time,
Mode switch 4 is set side, control time of digital switch group 1 Digital switch group 1
-1 to set the desired time, and set the operation pattern of the desired control equipment group corresponding to that time with operation pattern setting digital switch 1-2.
The BCD code is output on the memory 2 data path.

Next, by turning on the write/read switch 5, the control time setting digital switch group 1-
1 and operation pattern setting digital switch group 1-2 are stored in memory 2. Then, the selector 6 uses the signal from the address mode switch 4 as a control signal, selects the signal from the write/read switch 5, uses the signal as input, and outputs a pulse to the address counter 3.

Based on the output of the address counter 3, the setting data stored in the memory 2 is read out and sent to the matching circuit 11, the storage circuit 12, and the selector 7.

On the other hand, the clock section 10 includes a clock pulse generator 9.
Clock pulses are introduced from the clock section 10, and the clock section 10 counts the clock pulses and sends them to the matching circuit 11 and the selector 7.

Further, a signal from the mode switch 4 is introduced into the selector 7, and using this signal as a control signal, it selects the signal from the memory 2, that is, the setting data, and does not select the counting contents from the clock section 10.

When the selector 7 selects setting data, this setting data is displayed on the time display device 14.

On the other hand, at this time, the input pulse to the address counter 3 introduced from the selector 6 is a pulse generated by the operation of the write/read switch 5.

Next, by turning off the write/read switch 5, the selector 6 sends a pulse signal to the address counter 3.

As a result, the contents of the address counter 3 are incremented by "+1".

Next, the desired control time and operation pattern are set again in the same manner as above using digital switch group 1, and when the write/read switch 5 is turned on, this setting data is stored in the memory 2 at the address that has been incremented by 1. When the address counter 3 is stored and the write/read switch 5 is turned off, the address counter 3 is again incremented by 1.

By repeating this operation, the time can be set while visually checking it.

Next, to check whether the settings are as desired, turn the mode switch 4 to the confirmation side, turn the write/read switch 5 on and off once, and then proceed as described above. The address counter 3 is incremented by 1, and the contents of the memory 2 specified by the address counter 3 are
That is, the control times are displayed on the time display device 14 in the order in which they are set and can be confirmed.

Next, to operate as a normal timer, turn the mode switch 4 to the operating side.

As a result, the output of the scan oscillator 8 is selected by the selector 6 for the address counter 3, and the address counter 3 starts counting automatically and at high speed. The contents are selected and input, and the clock time is displayed.

Further, by setting the clock unit 10 to the correct time using a clock correction circuit (not shown), the normal operation mode is established.

In other words, the address counter 3 that measures at high speed
The matching circuit 11 constantly monitors the contents of the memory 2 specified by the momentary contents of the clock section 10, and if the contents of the memory 2 and the contents of the clock section 10 match, the memory 2 at the time of the match is The storage circuit 12 stores the contents of the memory 2 of the operation pattern of the control equipment group (not shown) stored at the address. The contents stored in the memory circuit 12 are outputted through the buffer circuit 13 to control external equipment and maintain this state until the coincidence circuit 11 generates the next pulse.

Now, FIG. 2 shows the configuration of an embodiment that more specifically shows the main parts of the electronic timer of this invention, which provide functions related to settings and confirmation. The invented electronic timer will now be described in more detail.

In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals, and RAM (random access memory) is used as memory 2.
The digital switch group 1 is connected to the data input terminal, and the data output terminal is connected to the input terminals of the matching circuit 11 and the selector 7, respectively.

In addition, the write/read switch 5 is a two-position momentary switch 501 and a NAND gate 50.
The movable terminal of the momentary switch 501 is grounded, and the fixed terminals N and C are connected to the first input side A of the NAND gate 502, and are connected to the power supply through a resistor. A fixed terminal NO of the switch 501 is connected to the second input side B of the NAND gate 503 and is connected to the power supply through a resistor.

The output side of NAND gate 502 is NAND gate 5
The output side of the NAND gate 503 is connected to the second input side B of the NAND gate 502.

The output side of the NAND gate 502 is connected to the second input side B of the NAND gate 601 in the selector 6, and the output side of the NAND gate 503 is connected to the first input side A of the two-input AND gate 15.

The second input side B of the AND gate 15 is connected to the first input side A of the OR gate 402 of the mode switch 4 (consisting of a three-stage rotary switch 401 and a two-input OR gate 402).

The output side of the AND gate 15 is connected to the write and memory bypass (both are valid at "1") terminals of the above-mentioned RAM, which is the memory 2.

The movable terminals of the three-stage rotary switch 401 in the mode switch 4 are connected to a power source, and the fixed terminals a, b, and c are each grounded through a resistor. And fixed terminal a,
b are connected to the first input terminal a and the second input terminal b of the OR gate 402, respectively.

A fixed terminal c of the rotary switch 401 is connected to a first input side i of a NAND gate 602 in the selector 6.

The output side of the OR gate 402 is a NAND gate 60
1 and the selector 7.

Selector 6 is a 2-input NAND gate 601-6
03, Nand Gate 602
The second input side B of is connected to the output side of the scan oscillator 8, and each output side of the NAND gates 601 and 602 is connected to the first input side A of the NAND gate 603.
They are respectively connected to the second input side B.

The output side of the NAND gate 603 is connected to the input side of the address counter 3.

The configuration of other parts is the same as in Figure 1, but
In the case of FIG. 2, the memory circuit 12 and buffer circuit 13 are omitted.

Note that the selector 7 is an AND-OR selector, the first input is a signal introduced from the memory 2 to the coincidence circuit 11, and the second input of the selector 7 is an input of the coincidence circuit 11 input from the clock section 10. The signal is the output of the clock section 10, and the control input is the output of the OR gate 402.

When this control input is "1", the first input is output, and when the control input is "0", the second input is selected and output to the clock display device 14.

Next, the operation of the embodiment shown in FIG. 2 will be described in detail.

First, when setting, when the movable contact of the rotary switch 401 of the mode switch 4 is switched to the fixed contact a side, a signal of "1" is input to the first input side A of the OR gate 402, and the second input side B is input. The signal becomes "0", and the output side of the OR gate 402 becomes "1".

Therefore, the first input side A of the NAND gate 601 is "1", and furthermore, the NAND gate 60
The first input side A of 2 is "0". The second input side B of the AND gate 15 is "1", and the control input of the selector 7 is "1".

Next, when the movable terminal of the momentary switch 501 of the write/read switch 5 is on the fixed terminal N, C side as shown in the figure, the first input side A of the NAND gate 502 is "0", and the first input side of the NAND gate 503 is "0". The input side A is “1”, and the second input side B is “1”
The output of the NAND gate 503 is "0".

Therefore, the second input side B of the NAND gate 502 becomes "0", and as a result, the NAND gate 50
The output of NAND gate 503 is "1", and the output of NAND gate 503 is "0".

That is, the first input side A of the AND gate 15 is "0", and the second input side B of the AND gate 15 is "1", as described above, so that the output of the AND gate 15 is "0",
The write memory bypass input of memory 2 becomes "0".

On the other hand, the first input side A of the NAND gate 601 is "1", the second input side "B" is "1", the output side of the NAND gate 601 is "0", and
The first input side of the NAND gate 602 is “0”
The second input side (b) repeats "1" and "0" at a higher speed than the output side of the scan oscillator 8, and the output side of the NAND gate 602 is "1".

As a result, the first input side A of the NAND gate 603 is "0" and the second input side B is "1",
Therefore, the output side of NAND gate 603 is "1".

If the address counter 3 is first reset to "0" by the output "1" of this NAND gate 603, the output of the address counter 3 will also become "0", the address 0 of the memory 2 will be designated, and the time The first input of the matching circuit 11 (the output of the memory 2) is input to the display device 14.

Next, when the desired control time and the like are set using the digital switch group 1, data is input to the data input side of the memory 2 encoded in BCD.

Next, when the movable terminal of the momentary switch 501 of the write/read switch 5 is switched to the fixed terminals N and O, the output side of the NAND gate 502 becomes "0" and the output side of the NAND gate 503 becomes "1".

As a result, both the first input side A and the second input side B of the AND gate 15 become "1", and the output side thereof also becomes "1", and the digital switch group 1 is set at address 0 of the memory 2. At the same time, this data is written to selector 7.
The time is then displayed on the time display device 14.

On the other hand, since the output side of NAND gate 502 became "0", at the same time NAND gate 601
The second input side B also changes from "1" to "0",
Therefore, the output of NAND gate 603 is "1"
However, since the address counter 3 counts at the rising edge of the input pulse, the contents of the address counter 3 do not change.
It is "0".

That is, data was written to address 0 of memory 2 by the above operation.

Next, when the movable terminal of the momentary switch 501 is switched to its original state, that is, to the fixed terminal N and C side, the output side of the NAND gate 502 becomes "0".
to "1", the output side of NAND gate 503 changes from "1" to "0", and AND gate 1
The output side of 5 changes from "1" to "0".

Further, the output side of the NAND gate 601 changes from "1" to "0", and the output side of the NAND gate 603 changes from "0" to "1".

Therefore, the address counter 3 is incremented by 1, and address 1 is designated in the memory 2.

In this way, at the time of setting, the movable terminal 401 of the rotary switch of the mode switch 4 is switched to the fixed terminal a side, the desired control time etc. are set with the digital switch group 1, and the momentary switch 501 of the write/read switch 5 is switched. By turning on and off, it is possible to write to the memory 2 while checking the address on the time display device 14 and automatically changing the address.

Next, when the movable terminal of the rotary switch 401 in the mode switch 4 is switched to the fixed terminal b side, the confirmation mode is entered.

That is, the first input side A of the OR gate 402 changes from "1" to "0", the second input side B changes from "0" to "1", but the output side of the OR gate 402 changes from "1" to "1". Yes, and the input to the address counter 3 is the same as at the time of setting.

Further, the control signal for the selector 7 is also the same as that at the time of setting.

On the other hand, since the second input side B of the AND gate 15 changes from ``1'' to ``0'', the output side of the AND gate 15 becomes ``0'', and the memory is no longer connected to the operation of the read/write switch 5. Writing to the memory 2 becomes impossible, and the contents of the memory 2 are sequentially displayed on the display device 14 in the order set by turning on and off the write/read switch 5, and can be visually confirmed.

Next, to operate as a normal timer, turn the rotary switch 401 of the mode switch 4.
When the movable terminal of is tilted toward the stator c side, OR gate 4
Both the first input side A and the second input side B of the NAND gate 601 become "0", and the first input side A of the NAND gate 602 becomes "0". 1'', the input on the second input side B of the NAND gate 601 becomes invalid, and the second input side B of the NAND gate 602 becomes valid.

That is, the second input side B of the NAND gate 603 is the inverted output of the scan oscillator 8, and the output of the NAND gate 603 is the inverted signal of the second input side B of the NAND gate 603.

Therefore, the high-speed pulses from the scan oscillator 8 are automatically input to the address counter 3 and counted.

On the other hand, the control signal of the selector 7 also changes from "1" to "0", the output of the clock section 10 is input to the time display device 14, and the time of the clock is displayed on the time display device 14.
The timer will now be displayed and the timer will be in normal operation mode.

In addition, in the above description of the configuration and operation, the time display was described, but the same applies to the display of the operation pattern of the control equipment group.

As described in detail above, according to this invention, the storage means stores the control time, the operation pattern of the control equipment group, etc., the reference clock pulse is counted by the clock section, and the counted contents of the clock section are stored in the storage device. By selecting one of the contents using the selector, the selected contents are displayed on the time display device, so when setting and checking the program, you can visually check it and automatically change the address while setting and checking. This eliminates the difficulty of setting, which is a disadvantage of conventional electronic timers, and since the display device for confirmation also serves as a time display device, the overall size can be reduced to a larger size. This has the advantage that it does not become expensive or expensive.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing one embodiment of the electronic timer of this invention, and Fig. 2 is a specific example showing in detail the circuit of the part related to program setting and confirmation in the electronic timer of this invention. FIG. 1...Digital switch group, 2...Memory,
3... Address counter, 4... Mode switch, 5... Write/read switch, 6, 7... Selector, 8... Scan oscillator, 9... Clock pulse generator, 10... Clock section, 11... Coincidence circuit, 12... memory circuit, 13... buffer circuit,
14...Time display device. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of utility model registration request] It consists of a group of digital switches that set the control time and a group of digital switches that set the operation pattern of the control equipment group, and a group of digital switches that generate a binary coded decimal code output, and the settings of this group of digital switches as the contents of the address counter. A mode switch having a setting and confirmation operation position for determining the operation mode of the timer at the address specified by and a first storage device for storing data at the timing specified by the position of the write/read switch, and a first memory device for counting reference clock pulses. a clock unit that obtains the time; a coincidence circuit that compares the contents of the clock unit with the contents of the first storage device; and a coincidence circuit that compares the contents of the clock unit with the contents of the first storage device; a second memory circuit that stores the operation patterns of the control equipment group stored in the memory device; and a second memory circuit that stores the operation patterns of the control equipment group stored in the memory device; and a second memory circuit that stores the operation patterns of the control equipment group stored in the memory device; comprising a selector for selecting one of the two, and a time display device for setting the time selected by the selector to be stored in the first storage device or displaying the time of the clock section,
An electronic timer characterized in that the control time can be set while visually checking, and the set contents can then be visually checked again.