JPS61102771A - solid state imaging device - Google Patents

solid state imaging device

Info

Publication number
JPS61102771A
JPS61102771A JP59226354A JP22635484A JPS61102771A JP S61102771 A JPS61102771 A JP S61102771A JP 59226354 A JP59226354 A JP 59226354A JP 22635484 A JP22635484 A JP 22635484A JP S61102771 A JPS61102771 A JP S61102771A
Authority
JP
Japan
Prior art keywords
drain
depletion layer
principle
vertical
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59226354A
Other languages
Japanese (ja)
Inventor
Sumio Terakawa
澄雄 寺川
Toshiyuki Kozono
利幸 小園
Masahiro Susa
匡裕 須佐
Koji Senda
耕司 千田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP59226354A priority Critical patent/JPS61102771A/en
Publication of JPS61102771A publication Critical patent/JPS61102771A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/15Charge-coupled device [CCD] image sensors
    • H10F39/158Charge-coupled device [CCD] image sensors having arrangements for blooming suppression

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To remove the occurrence of smearing charges, which are generated in a conventinoal solid-state image pickup sensor element, in principle or to decrease said occurrence to a large extent, by providing a photoelectric conver sion ele- ment part and vertical and horizontal transfer parts, and forming the vertical transfer part on a substrate having an SOI structure. CONSTITUTION:A drain 4 is formed on an SiO2 film 13, and a so-called an SOI structure is formed. In the drain part 4, which is formed on the SiO2 film 13, a depletion layer is not present in principle since N type impurities are diffused in the entire surface of the drain part 4. In the silicon and the drain part 4 beneath the gate electrode 14, however, some depletion layer is formed. In a conventional drain, which does not use the SOI structure, the depletion layer is inevitably formed. In the drain part 4 with this structure, the depletion layer can be completely eliminated, except some depletion layer between the gate electrode 14 and the drain part 4. The operation, in which smearing charges l<-> are not accumulated in principle, can be realised.

Description

【発明の詳細な説明】 童業上の利用分野 本発明は固体撮像装置に関するものである。[Detailed description of the invention] Fields of use in childcare The present invention relates to a solid-state imaging device.

従来例の構成例とその問題点 最近、MaS形、CCD形、CPD形などの固体撮像装
置の開発が進み、解像度、感度などの点から見て撮像管
に匹敵するものが実用化されている。たとえば、ブルー
ミングについては固体撮像装置の光電変換部を基板と反
対導電型のウェル内に形成し、基板に所定の電圧を印加
して、生じたブルーミング電荷を基板に排出することに
より実用土問題のないレベルに低減され゛ている。
Examples of conventional configurations and their problems Recently, development of solid-state imaging devices such as MaS type, CCD type, and CPD type has progressed, and devices comparable to image pickup tubes in terms of resolution, sensitivity, etc. have been put into practical use. . For example, regarding blooming, the photoelectric conversion part of the solid-state imaging device is formed in a well of the opposite conductivity type to the substrate, a predetermined voltage is applied to the substrate, and the generated blooming charge is discharged to the substrate. It has been reduced to a level that does not exist.

この場合に採用されたウェル構造はMOS形、CCD形
(I L−CCD形)、CPv形においてはそれぞれ第
1図(a) 、 (h) t (c) K示した構造を
使用している。
The well structures adopted in this case are the structures shown in Figures 1 (a) and (h) t (c) K for the MOS type, CCD type (IL-CCD type), and CPv type, respectively. .

第1図において、1はn型基板、2はPウェル3はフォ
トダイオード、4はドレイン、6はアルミ遮光膜、6は
LOCO5酸化膜、7はNSG喚、8.9けチャンネル
ストッパー、1Qはアルミ信号線、11は垂直転送CO
D、12は垂直伝送線である。(a)のMOS形ではP
ウェル2は所定の基板電圧でVi空乏化されない濃度を
使っている。(b)のILo−CCD形ではフォトダイ
オード3の下のPウェル2は所定の基板電圧で空乏化さ
れるが、垂直転送部11の下は空乏化されないウェル構
造を採用している。(C)のCPD型では所定の基板電
圧で空乏化されるウェル濃度を採用している。これらは
いずれも飽和元以上で生じるブルーミング電荷の低減あ
るいは除去に対し有効な構造となっている。しかしなが
ら、飽和光以下で生じるスメアについては、ウェル構造
を用いることにより一定の低減効果はあるものの、その
構造上限界があり、実用上問題となっている。
In Figure 1, 1 is an n-type substrate, 2 is a P well, 3 is a photodiode, 4 is a drain, 6 is an aluminum light shielding film, 6 is a LOCO5 oxide film, 7 is an NSG cap, 8.9 is a channel stopper, and 1Q is a Aluminum signal line, 11 is vertical transfer CO
D, 12 is a vertical transmission line. In the MOS type (a), P
Well 2 uses a concentration that does not cause Vi depletion at a predetermined substrate voltage. In the ILo-CCD type shown in (b), the P well 2 under the photodiode 3 is depleted at a predetermined substrate voltage, but the well structure under the vertical transfer section 11 is not depleted. The CPD type shown in (C) employs a well concentration that is depleted at a predetermined substrate voltage. All of these structures are effective in reducing or eliminating blooming charges that occur above the saturation point. However, although the use of a well structure has a certain reduction effect on smear generated under saturated light, there is a limit due to the structure, and this is a practical problem.

(a)のMOS形ではチャンネルストッパー8のドレイ
ン近傍に斜め光入射で生じた電荷e−や、基板深部で生
じた電荷e−は、ウェルが空乏化していないことなどに
より、基板1に効果的に排出されることができず、矢印
で示すように拡散しドレイン4の空乏層に蓄積され、結
局スメア電荷となってし1う。
In the MOS type shown in (a), the charge e- generated near the drain of the channel stopper 8 due to oblique light incidence and the charge e- generated deep in the substrate are not effectively applied to the substrate 1 because the well is not depleted. The charge cannot be discharged to the drain 4 and is diffused as shown by the arrow and accumulated in the depletion layer of the drain 4, eventually becoming a smear charge.

((9)のIL−CCD形の場合も、斜め光入射で生じ
た電荷のe−や基板1に生じた電荷e−が矢印で示すよ
うに拡散し、垂直転送部11の空乏層に蓄積されスメア
電荷となってし棟う。(C)のCPD形の場合において
も(−)のMOS形と同様に、斜め光入射で生じた電荷
e−や、基板深部で生じた電荷e−が矢印で示すように
拡散してドレイン4の空乏層に捕えられ、スメアとなっ
てしまう。
(Also in the case of the IL-CCD type (9), the charge e- generated by oblique light incidence and the charge e- generated in the substrate 1 diffuse as shown by the arrow and accumulate in the depletion layer of the vertical transfer section 11. In the case of the CPD type (C), as well as the MOS type (-), the charge e- generated by oblique light incidence and the charge e- generated deep in the substrate are As shown by the arrow, it diffuses and is trapped in the depletion layer of the drain 4, resulting in a smear.

以上のように、従来の固体撮1象装置に訃いては、原理
的にスメア電荷を生じさせない様にすることけできなか
った。
As described above, in the conventional solid-state imaging device, it is impossible in principle to prevent the generation of smear charges.

発明の目的 本発明は上記欠点に鑑み、従来の固体rRf象素子に生
じるスメア電荷を原理的に発生するのを除去するか、あ
るいは大巾に低減できるような構造を備えた固体撮像装
置を提供すること(である。
OBJECTS OF THE INVENTION In view of the above drawbacks, the present invention provides a solid-state imaging device having a structure that can theoretically eliminate or significantly reduce the smear charge generated in conventional solid-state rRf quadrants. It is to be.

発明の構成 この目的を達成するために、本発明の固体撮像装置は、
行列状に配列された光電変換素子部と、前記光電変換素
子部で光電変換された光信号電荷を時系列的に読み出す
垂直及び水平の転送部とを備えるとともに、前記垂直転
送部がSOI構造を有する基板上に形成されて構成され
ている。
Structure of the Invention In order to achieve this object, the solid-state imaging device of the present invention has the following features:
It includes a photoelectric conversion element section arranged in a matrix, and vertical and horizontal transfer sections for reading out optical signal charges photoelectrically converted in the photoelectric conversion element section in time series, and the vertical transfer section has an SOI structure. The device is formed on a substrate having a structure.

実施例の説明 以下、本発明の実施例について、CPD形を例にとって
、図面を参照しながら説明する。第2図は本発明の一実
施例の断面構造を示す。nチャンネルの場合について述
べる。
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking a CPD type as an example. FIG. 2 shows a cross-sectional structure of an embodiment of the present invention. The case of n-channel will be described.

第2図において、1はn型基板、2f′iPウエル、3
はPウェル上に形成されたフォトダイオード、4けドレ
イン、5はアルミ遮光膜、6は素子間分離のLOCO3
厚膜、7はNSG膜、12は垂直伝送線のAI電極、1
3はSiO2膜、14Vi垂直MOSトランジスタのポ
リ7リコンゲート、16はSG膜である。
In FIG. 2, 1 is an n-type substrate, 2f'iP well, 3
is a photodiode formed on the P well, 4 is a drain, 5 is an aluminum light-shielding film, and 6 is LOCO3 for isolation between elements.
Thick film, 7 is NSG film, 12 is AI electrode of vertical transmission line, 1
3 is a SiO2 film, a poly7 silicon gate of a 14Vi vertical MOS transistor, and 16 is an SG film.

図から分かるように、ドレイン4はSi○2膜13膜上
3形成され、いわゆるS OI (Semi cond
uctoron In5alator構造が形成されて
いる。この構造は、先ずn型シリコン基板1の表面を酸
化した後、生成した5iQ2膜を選択エッチして、島状
にS iO2@13を残す。S i02膜13の上から
シリコン基板1の表面にポリシリコンを被着した後アニ
ールにより単結晶化させる。
As can be seen from the figure, the drain 4 is formed on the Si○2 film 13, and is a so-called SOI (Semi-cond
A uctoron In5alator structure is formed. In this structure, first, the surface of an n-type silicon substrate 1 is oxidized, and then the generated 5iQ2 film is selectively etched to leave SiO2@13 in the form of islands. After polysilicon is deposited on the surface of the silicon substrate 1 from above the Si02 film 13, it is made into a single crystal by annealing.

単結晶層の中にドレイン4、フォートダイオード3など
?形成する。
Drain 4, fort diode 3, etc. in the single crystal layer? Form.

S 102  膜13上Vこ形成されたドレイン部4は
n形不純物が全面的に拡散されているので、空乏層下の
ノリコノとドレイン4 t’rb千の空乏層が形成さt
するだけである。従って、従来のSOIを用いないドレ
インでは必ず空乏層が不可避的に形成されるのに対し本
構造のドレイン4は、ゲート電極14とドレイン4との
間の若干の空乏1ili1ヲ除いて、全く空乏層を無く
することができ、スメア電荷e−を原理的に集積しない
作用を実現できる。また、ドレイン4下のS 102膜
13は基板1の深部で生じたスメア電荷e−をドレイン
4から完全に分前できて、矢印の方向に動いてドレイン
4に到達するのを避けることができる。いずれにしても
従来のドレイン構造の持つスメア蓄積作用を事実上、原
理的に無くすることができ、固体撮(象素子の最大欠点
の一つであるスメアを生じなくすることができるう また、ドレイン部の空乏層を無くすることができるため
、垂直伝送線客用をも大巾に低減でき、垂直部から生じ
るノイズを大巾に低減することも同時に可能となる。
S 102 Since n-type impurities are diffused all over the drain region 4 formed on the film 13, a depletion layer of 1,000 is formed below the depletion layer.
Just do it. Therefore, while a depletion layer is inevitably formed in conventional drains that do not use SOI, the drain 4 of this structure has no depletion at all, except for a small amount of depletion between the gate electrode 14 and the drain 4. It is possible to eliminate the layer, and it is possible to realize an action in which smear charges e- are not accumulated in principle. In addition, the S102 film 13 under the drain 4 can completely remove the smear charge e- generated deep in the substrate 1 from the drain 4, thereby preventing it from moving in the direction of the arrow and reaching the drain 4. . In any case, the smear accumulation effect of the conventional drain structure can be virtually eliminated in principle, and smear, which is one of the biggest drawbacks of solid-state sensors, can be eliminated. Since the depletion layer in the drain section can be eliminated, the vertical transmission line for customers can also be greatly reduced, and at the same time, it is also possible to greatly reduce the noise generated from the vertical section.

また、IL−COD構成において、垂直CODをS○工
上に形成することにより、基板深部から拡散により垂直
CODに蓄積されるスメア電荷を完全になくすることが
できる。MOS形に適用すること(′こよってもスメア
を原理的に無くすことが可能となる。
Furthermore, in the IL-COD configuration, by forming the vertical COD on the S○ process, it is possible to completely eliminate smear charges that are accumulated in the vertical COD by diffusion from the deep part of the substrate. By applying it to a MOS type, it becomes possible to eliminate smear in principle.

発明の効果 以上の様に本発明は固体撮浄素子における最大の欠点で
あるスメアを原理的に完全に除去、あるいは大巾に低減
する事が可能となり、その実用的効果は大なるものがあ
る。
As can be seen from the effects of the invention, the present invention makes it possible in principle to completely eliminate or greatly reduce smear, which is the biggest drawback in solid-state imaging devices, and has great practical effects. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a) t (b) 、 (C)はそれぞれ従来
のMOS形、CCD形、CPD形固体撮障装置の断面構
造を示す断面構造図、第2図は本発明の一実施例を示す
1面構造図でおる。 1・・・n型基板、2・・・・Pウェル、3・・・・・
・フォトダイオード、4・・・ ・ドレイン、5・・・
・・・アルミ遮光膜、6・・・・LOCO3酸化膜、7
・・・・・・NSG膜、12 ・・・垂直伝送線のAI
電極、13・・・・・・SiO3摸、14・・・・・・
垂直MO3トラ7ジスタのゲート電極。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名菓 
1 図
Figures 1(a), t(b), and (C) are cross-sectional structural diagrams showing the cross-sectional structures of conventional MOS type, CCD type, and CPD type solid-state imaging devices, respectively, and Figure 2 shows one embodiment of the present invention. This is a one-page structural diagram shown. 1...N type substrate, 2...P well, 3...
・Photodiode, 4... ・Drain, 5...
...Aluminum light shielding film, 6...LOCO3 oxide film, 7
・・・・・・NSG film, 12 ・・・AI of vertical transmission line
Electrode, 13... SiO3 model, 14...
Gate electrode of vertical MO3 transistor. Name of agent: Patent attorney Toshio Nakao and one other name
1 figure

Claims (1)

【特許請求の範囲】[Claims]  m行n列の行列状に配列された光電変換素子部と、前
記光電変換素子部で光電変換された光信号電荷を時系列
的に読み出す垂直及び水平の転送部を備え、前記垂直転
送部が絶縁層の表面に形成されていることを特徴とする
固体撮像装置。
A photoelectric conversion element section arranged in a matrix of m rows and n columns, and vertical and horizontal transfer sections for reading out optical signal charges photoelectrically converted in the photoelectric conversion element section in time series, the vertical transfer section comprising: A solid-state imaging device characterized by being formed on the surface of an insulating layer.
JP59226354A 1984-10-26 1984-10-26 solid state imaging device Pending JPS61102771A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59226354A JPS61102771A (en) 1984-10-26 1984-10-26 solid state imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59226354A JPS61102771A (en) 1984-10-26 1984-10-26 solid state imaging device

Publications (1)

Publication Number Publication Date
JPS61102771A true JPS61102771A (en) 1986-05-21

Family

ID=16843838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59226354A Pending JPS61102771A (en) 1984-10-26 1984-10-26 solid state imaging device

Country Status (1)

Country Link
JP (1) JPS61102771A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62296553A (en) * 1986-06-17 1987-12-23 Matsushita Electronics Corp Light receiving element
JPH0236568A (en) * 1988-07-27 1990-02-06 Fuji Xerox Co Ltd Semiconductor device and image sensor driving device using said device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62296553A (en) * 1986-06-17 1987-12-23 Matsushita Electronics Corp Light receiving element
JPH0236568A (en) * 1988-07-27 1990-02-06 Fuji Xerox Co Ltd Semiconductor device and image sensor driving device using said device

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