JPS61105144A - Pseudo reference burst generator - Google Patents

Abstract

PURPOSE:To transmit a desired control signal to a slave station device and to obtain an economical pseudo reference burst generator by providing a reference burst generating circuit generating a reference burst and a modulation circuit modulating the reference burst and outputting the result and giving an output signal of the modulation circuit to a time division multiple address device as a test signal. CONSTITUTION:A system clock signal 101 is given to a frame counter 2, a reference burst synthesis circuit 3 and a clock input CLK of a modulation circuit 32 from a system block oscillator 1 being an oscillator of a symbol rate frequency. The system block signal 101 is subject to frequency division and becomes a frame pulse signal 102 corresponding to the TDMA frame period is given to a frame pulse input of a reference burst synthesis circuit 3 from the output TC of the frame counter 2. A burst gate signal 103 corresponding to the reference burst length is given to the modulation circuit 32 from the reference burst synthesis circuit 3, further a transmission data signal 109 is given to the modulation circuit 32 from an OR gate 11 and a reference burst 110 is given to a time division multiple address device (not shown) from the modulation circuit 32.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pseudo-reference burst generator for testing time division multiple access equipment for satellite communications. In particular, the present invention relates to a pseudo-reference burst generator that enables efficient and economical testing and maintenance of a single time division multiple access device.

The time division multiple access (hereinafter referred to as TDMA) communication method is a TDMA communication method determined by a reference synchronization burst sent out by a reference station.
In this method, each slave station transmits a burst signal at a predetermined timing based on a DMA frame, and performs communication by controlling the bursts so that they do not overlap with each other.

[Conventional technology]

In the operation of TDMA communication equipment, it is necessary to periodically confirm that there is no deterioration of the transmit signal system and the receive signal system. Conventionally, this test uses a pseudo reference station device that generates a signal with the same shape as the reference burst. was. This pseudo reference station device receives synchronization signals (R[EF IJW,
A reference burst containing a reference unique word (Reference Unique Word) is sent out at TDMA frame intervals, and a read-only memory (ROM, Read
0nly Memoy) was selected using a switch and sent out.

[Problem that the invention seeks to solve]

However, recently, TDMA communication systems are composed of a small number of reference stations (usually 1 to 3) and a large number of slave stations, so even if the number of base station devices increases, if the slave station devices can be simplified, TDMA communication Taking advantage of the feature that improves the economic efficiency of the entire system, the current use, standby switching, and transmission synchronization control of each slave station is performed by individually selecting the slave station to be controlled using the control channel set in the reference burst. It has become.

For this reason, with conventional pseudo reference station devices that only have the function of selecting and transmitting a control code prepared in advance using a switch, a problem has arisen in that only a small portion of the operation of the slave station device can be tested.

FIG. 8 is a block diagram of a conventional test method for a time division multiple access device. To solve the above problem, as shown in Fig. 8, the transmitting signal system of the station performing maintenance work is separated from the antenna 50, only the receiving signal system is connected to the antenna 50, and the transmitting signal of the own station is combined with this received signal. TDM, A device 3
It is possible to take a method in which the reference station actually controls this station by supplying it to the reception signal system of No. 5 and confirms its operation.

However, with this method, the work must be done in collaboration with the reference station, which increases the number of workers and requires multiple slave stations to work in parallel.If a failure occurs in a slave station, it is difficult to carry out tests to determine the cause of the problem. Therefore, there are problems that affect the maintenance work of other slave stations.

In addition, if the slave station device has a working standby configuration,
In order to test only the spare machine, it is necessary to use a test control code to distinguish between the working machine, so there is a problem that it does not necessarily guarantee complete operation with the working control signal. There is.

The present invention solves the above-mentioned problems and aims to provide an economical pseudo-reference burst generator that can send a desired control signal to a slave station device.

[Means for solving problems]

A first invention includes a reference burst generation circuit that generates a reference burst, and a modulation circuit that modulates and outputs the reference burst, and means for providing an output signal of the modulation circuit as a test signal to a time division multiple access device. In the pseudo-image reference burst generation device, the reference burst generation circuit includes:
means for generating a frame pulse signal corresponding to a time division multiple access frame period; and outputting a burst gate signal of a reference burst length to the modulation circuit by the frame pulse signal, and generating a carrier timing recovery code, a unique word, and a control signal. Reference burst synthesis means for outputting a control channel gate signal indicating a channel portion and a symbol address signal for the control channel portion; a plurality of storage means for storing patterns of the control channel portion; and changing the contents of the storage means. a write control means; a synchronization signal generation means for outputting a synchronization signal synchronized with a cycle that is an integral multiple (but not less than 1) of the time division multiple access frame cycle using the frame pulse signal; and the synchronization signal. selecting means for inputting the control channel gate signal and the symbol address signal into one of the plurality of storage means and connecting the other storage means to the write control means; The present invention is characterized in that it includes means for outputting a logical sum of the output of the recording means, the carrier timing recovery code, and the unique word to the modulation circuit.

A second invention includes a reference burst generation circuit that generates a reference burst, and a modulation circuit that modulates and outputs the reference burst, and means for providing an output signal of the modulation circuit as a test signal to a time division multiple access device. In the pseudo-reference burst generation device, the reference burst generation circuit includes:
means for generating a frame pulse signal corresponding to a time division multiple access frame period; a dividing means for dividing the frequency of the frame pulse signal; and outputting a burst gate signal of a reference burst length to the modulation circuit using the frame pulse signal. , a carrier timing recovery code, a unique word,
Reference burst synthesis means for outputting a control channel gate signal indicating a control channel portion and a symbol address signal for the control channel portion; a plurality of storage means for storing patterns and transmission orders of the control channel portion; and the storage means. outputting a synchronization signal synchronized with a cycle that is an integral multiple (but not less than 1) of the time division multiple access frame cycle using a write control means for changing the contents of the frame and an output signal of the frequency division means. a synchronization signal generating means; inputting the control channel gate signal and the symbol address signal into one of the plurality of storage means according to the synchronization signal; a selection means to be connected; a control means for controlling the output of the one storage means according to the output signal of the frequency division means; and an output of the one storage means controlled by the control means and the carrier wave timing reproduction code. and means for outputting a logical sum with the unique word and the unique word to the modulation circuit.

[For production]

In the present invention, a frame counter generates a frame pulse signal corresponding to a TDMA frame period, and a reference burst synthesis means uses this frame pulse signal to provide a burst gate signal having a reference burst length to a modulation circuit. A synchronization signal synchronized with a period that is an integral number (1 or more) times the TDMA frame period from the synchronization signal generation means is used to switch the selection means to one of the plurality of storage means for storing the pattern of the control channel part. , a control channel gate signal and a symbol address signal from the reference burst synthesis means are input, and the output of this one storage means and the carrier timing recovery code and unique word from the 59 burst synthesis means are ORed into a modulation circuit. Output to. Further, the selection means connects another storage means to the write i control means so that the contents can be changed. As described above, a desired control signal can be sent to the slave station device without control from the reference station, and all functions of the slave station device can be checked.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a pseudo-reference burst generator according to an embodiment of the present invention. In FIG. 1, a system clock signal 101 from a system clock oscillator 1, which is an oscillator with a symbol rate frequency, is connected to a clock input CLK of a frame counter 2, a reference burst synthesis circuit 3, and a modulation circuit 32. Frame counter 2 output TC
A frame pulse signal 102 corresponding to the TDMA frame period obtained by frequency-dividing the system clock signal 101 from the reference burst synthesis circuit 3 is connected to the frame pulse input of the reference burst synthesis circuit 3.

A burst gate signal 103 corresponding to the reference burst length is connected from the reference burst synthesis circuit 3 to the modulation circuit 32 . Further, a control channel gate signal 105 indicating the control channel portion and a symbol address signal 106 of the control channel portion from the reference burst synthesis circuit 3 are respectively connected to the input A of the selection circuit 4.

The output X of the selection circuit 4 is connected to the input of the memory circuit 5, and the output Y is connected to the input of the memory circuit 6. Write control circuit 7
The output of is connected to the input B of the selection circuit 4. Memory circuit 5
and 6 are connected to one input of AND gates 8 and 9. One terminal of the changeover switch 12 is grounded, and the other terminal is connected to the input C of the flip-flop 13 and one terminal of the resistor. The input of flip-flop 13 is connected to output d, and the output d is connected to flip-flop 1.
Connected to input 4. Output T of frame counter 2
A frame pulse signal 102 is branched from C and connected to input C of flip-flop 14. The output signal 108 from the output Q of the flip-flop 14 is the input S of the selection circuit 4.
EL is input to the other input of the AND gate 9 and the inverter IO, and the output of the inverter IO is connected to the other input of the AND gate 8.

A data signal 104 corresponding to a carrier timing recovery code and a unique word from the reference burst synthesis circuit 3 and a control channel data signal 107 from the AND gate 8 or 9.
are respectively connected to the inputs of the OR gate 1).

Here, the output signal 108 of the flip-flop 14 is rO
In the case of J, the selection circuit 4 connects input A and output X, and connects input B and output Y. Therefore, the memory circuit 5
A control channel gate signal 105 indicating a control channel portion and a symbol address signal 106 from the reference burst synthesis circuit 3 are connected to the control channel gate signal 105 and a symbol address signal 106 indicating the control channel portion from the reference burst synthesis circuit 3. Connected to the input of the OR gate. The memory circuit 6 is connected to the write control circuit 7 and its contents can be rewritten. When the output signal 108 is "1", the selection circuit 4 connects the input A and the output Y, and connects the input B and the output X. Therefore, storage circuit 5 and storage circuit 6 are switched. The transmission data signal 109 from the OR gate 1) is connected to the modulation circuit 32, and the reference burst 1)0 from the modulation circuit 32 is connected to a time division multiple access device (not shown).

The operation of the pseudo reference burst generator having such a configuration will be explained.

FIG. 2 is a block diagram of a test method using the pseudo-reference burst generator of the present invention. In Figure 2, 31
32 is a pseudo reference burst pattern generation circuit; 32 is a modulation circuit;
33 is a pseudo-reference burst generator, 34 is a hybrid circuit, 35 is a TDMA device, 36 is a demodulation circuit, 37 is a reception logic circuit, 38 is a control circuit, 39 is a transmission logic circuit, and 40 is a modulation circuit.

Figure 3 shows T when the test is conducted using the test method shown in Figure 2.
FIG. 3 is a configuration diagram of a DMA frame. In Figure 3,
R8 indicates a reference burst, and LB indicates a slave burst.

FIG. 4 is a configuration diagram of a reference hearth 1-RB not shown in FIG. 3. In FIG. 2, the pseudo reference burst generator 33 generates the reference hearth 1-RB shown in FIG. The contents of the included control channel C3 are decoded and the slave station burst LB is transmitted. For example, when synchronizing transmission using this method, the TDMA device 35
The reference burst RB shown in the figure is received, the carrier wave and the reception clock are regenerated by the carrier wave timing recovery code CT shown in FIG. 4, the unique word circle shown in FIG. The control channel cs is decoded as a reference. The pseudo-reference burst generator 33 sends a transmission permission and a delay measure that defines the difference between the transmitted frame and the received frame to the control channel cs, so that the TDMA device 35 transmits data at a position delayed by D symbols from the beginning of the received frame. The beginning of the frame is defined, and the slave station bursts and sends B at a timing delayed by the number of symbols specified by the line pattern.

In the test method shown in FIG. 2, the value of the delay ID is D=N frame length - D', where D' is the signal delay time from transmission to reception of the TDMA device 35, and the slave burst LB is determined by the line pattern. will be sent to the specified location. Generally, it must be an integer of 1 or more.

FIG. 5 is a time chart of signals of the pseudo reference burst generator of the present invention. In FIG. 5, the same numbers as those shown in FIG. 1 indicate the same signals.

In FIG. 1, a system clock oscillator 1 is an oscillator with a frequency equal to the symbol rate, and a system clock signal 101
is distributed to the frame counter 2, reference burst synthesis circuit 3, and modulation circuit 32.

The frame counter 2 divides the frequency of the system clock signal 101 and generates a frame pulse signal 102 corresponding to the TDMA frame period.

59 burst synthesis circuit 3 receives this frame pulse signal 1.
02 as a trigger, which corresponds to the reference burst length. A burst gate signal 103, a data signal 104 corresponding to a carrier wave and timing recovery code 201 and a unique word 202, and a gate signal 1 with no control channel portion shown.
05 and the symbol address signal 106 of this part are output.

When the input SEL is "0", the selection circuit 4 connects the input A signal to the output X, and connects the input B signal to the output Y. Further, when the input SEL is "1", the signal of the input A is connected to the output Y, and the signal of the input B is connected to the output X.

Therefore, when the output signal 108 of the flip-flop 14 is "0", the reference burst synthesis circuit 3 outputs it to the storage circuit 5. Gate signal 10 indicating control channel part
5 and symbol address signal 106 are supplied, and the pattern written in memory circuit 5 is outputted as control channel data signal 107 through AND gate 8. The control channel data signal 107, the carrier/wave timing recovery code CT, and the data signal 104 corresponding to the unique word U- are combined in the OR game H1 and supplied to the modulation circuit 32 as a transmission data signal 109.

The modulation circuit 32 performs modulation and tuning corresponding to the transmission data signal 109 only during the period when the burst gate signal 103 is "1", and outputs the reference burst RB.

The memory circuit 6 is connected to the write control circuit 7 and its contents can be rewritten when the output signal 108 of the flip-flop 14 is "0".

Therefore, write the control code you want to output next to the control circuit 7.
When the changeover switch 12 is momentarily turned on, this pulse is inputted to the flip-flop 13 as a clock signal, and the output Q of the flip-flop 13 is inverted. This signal is retimed with the frame pulse signal 102 and supplied as a selection signal to the storage circuit 5.6.

As mentioned above, by switching the memory circuits 5 and 6 in synchronization with the frame timing, the memory circuits 5 and 6 are not switched while the reference burst is being transmitted, so that meaningless control codes are not transmitted. You can prevent this from happening.

In order to avoid the influence of errors in the transmission path, the control channel C3 may be transmitted at a cycle that is an integral multiple of a frame, such as when it is repeatedly transmitted. At this time, in order to define the timing multiplied by this integer (1 or more), a circuit is added to divide the frame pulse 102, and the output of this frequency dividing circuit is input to the clock input of the flip-flop 14 and to the selection circuit 4. It is sufficient to supply the memory circuit 5 and the memory circuit 6 through the memory circuit 5 and the memory circuit 6. If there are three or more sets of memory circuits, the number of bits of the memory circuit selection signal 108 may be increased.

FIG. 6 is a block diagram of a similar reference burst generator according to another embodiment of the present invention. In FIG. 6, the same numbers as those shown in FIG. 1 indicate the same circuits and signals. 2
0 is a change point detection circuit, and the signal applied to the input IN is "0".
” to rlJ or from “1” to “0”, a short “1” pulse is output to the output OUT. 21 is a frequency dividing circuit that divides the frequency of the frame pulse signal 102;
22 is a frequency dividing circuit that further divides the frequency of this frequency-divided pulse.

In the case of the embodiment shown in FIG. 6, the pattern to be transmitted to the control channel, the number of times this pattern is to be repeatedly transmitted, and the repetition control code are written in the memory circuit 5 and the memory circuit 6.

FIG. 7 is a diagram showing the contents of the memory circuit.

In FIG. 7, 301 is a control channel pulse, and N bits constitute one word. An N-bit control channel pulse is transmitted in one frame and an integer number of one frame (
However, the number shall be 2 or more. ) in some cases. 302 is a repetition control code, and 303 is the number of repetitions. In this case, the contents of the memory circuit are N+ as shown in FIG.
One word constitutes one block. Repeat control code 3
When 02 is “00”, it indicates that the control channel pulse 301 is a control channel pattern, and when it is “01”, V is applied to this word the number of times specified in the number of repetitions 303.
After repeatedly sending control channel break (E<N via), it moves on to processing the next block, and when it is "1o", it moves on to processing the first block after finishing that block processing, and when it is "1)", it moves on to processing the first block. Define the block to continue processing until it is reset.

In this way, the repeat control code 302 is placed at the beginning of the N+1 word.
writes “01”, “10” or “1)”, defines the processing of this block, repeats the following N words, and sets the control code 302 to “oO” to the control channel pattern 30.
Write the control channel Bakun to be sent to 1. To repeatedly send out the same control channel interrupt, the repetition number 303 is sent to the frequency divider circuit 22 by the repetition number cent signal shown in FIG. When the content becomes "0" after each subtraction, the block transition signal 124 shown in FIG. 6 is used to notify the storage circuit 5 or 6, and the process proceeds to the next block.

The above explanation assumes that only one reference burst is sent out, but a pulse separated by an appropriate amount of time is output from the frame counter, and this pulse is used to drive the reference burst synthesis circuit to generate multiple reference bursts. It can also be implemented in such a way that it occurs.

Furthermore, the memory circuit can be equivalently implemented as a plurality of memory circuits by using only one piece of hardware and assigning separate addresses.

The present invention allows the device to be miniaturized by applying a microprocessor.

〔Effect of the invention〕

As explained above, the present invention economically enables the slave device to
This has an excellent effect in that all control operations received from the reference station can be tested and confirmed without the control of the reference station. Therefore, it has a very large effect on improving the reliability of TDMA satellite communication. Furthermore, since the equipment to be tested can be tested completely separated from the satellite system, the current communication system will not be affected by erroneous operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a pseudo-reference burst generator according to an embodiment of the present invention. FIG. 2 is a block diagram of a test method using the pseudo-reference burst generator of the present invention. FIG. 3 is a diagram showing the configuration of the time division multiple access frame. FIG. 4 is a configuration diagram of the reference burst. FIG. 5 is a time chart of each signal of the pseudo reference burst generator of the present invention. FIG. 6 is a block diagram of a pseudo-reference burst generator according to another embodiment of the present invention. FIG. 7 is a diagram showing the contents of the memory circuit. FIG. 8 is a block diagram of a conventional test method for a time division multiple access device. ■...System clock oscillator, 2...Frame counter, 3...Reference burst synthesis circuit, 4...Selection circuit, 5.6...Storage circuit, 7...Write control circuit,
8.8', 9.9'...AND gate, 10...Inverter, 1)...OR gate, 12...Selector switch, 13.14...D type flip-flop,
20... Change point detection circuit, 21.22... Frequency division circuit, 31... Pseudo reference burst pattern generation circuit, 32.
...Modulation circuit, 33...Pseudo reference burst generator,
34... Hybrid circuit, 35... Time division multiple access circuit, 36... Demodulation circuit, 37... Reception logic circuit, 38... Control circuit, 39... Transmission logic circuit, 4o
... Modulation circuit, 50 ... Antenna, 101 ... System clock signal, 102 ... Frame pulse signal, 103 ... Burst gate signal, 104 ... Corresponds to carrier wave timing recovery code and unique word. 105...Gate signal indicating control channel part, 106...Symbol address signal of control channel part, 107...Control channel data signal, 108
... Output signal of flip-flop (14), 109.
...Transmission data signal, 120...Changing point detection signal, 1
21, 122... Frequency division signal, 123... Repeat count cent signal, 124... Block transition signal, CS/
...Control channel, CT...Carrier timing recovery code, LB...Slave station burst, RB...Reference burst, Listen...Unique word.

Claims (2)

[Claims] (1) It includes a reference burst generation circuit that generates a reference burst, and a modulation circuit that modulates and outputs the reference burst, and includes means for providing an output signal of the modulation circuit as a test signal to a time division multiple access device. In the pseudo reference burst generation device, the reference burst generation circuit includes means for generating a frame pulse signal corresponding to a time division multiple access frame period, and the frame pulse signal causes a burst gate signal of a reference burst length to be transmitted to the modulation circuit. reference burst synthesis means for outputting a carrier timing recovery code, a unique word, a control channel gate signal indicating a control channel portion, and a symbol address signal for the control channel portion; and storing a pattern of the control channel portion. a plurality of storage means; a write control means for changing the contents of the storage means; a synchronization signal generating means for outputting a synchronization signal; and inputting the control channel gate signal and the symbol address signal into one of the plurality of storage means according to the synchronization signal, A pseudo-standard comprising: a selection means connected to a write control means; and means for outputting a logical sum of the output of the one storage means, the carrier timing recovery code and the unique word to the modulation circuit. Burst generator. (2) It includes a reference burst generation circuit that generates a reference burst, and a modulation circuit that modulates and outputs the reference burst, and includes means for providing an output signal of the modulation circuit as a test signal to a time division multiple access device. In the pseudo reference burst generation device, the reference burst generation circuit includes means for generating a frame pulse signal corresponding to a time division multiple access frame period, frequency dividing means for dividing the frequency of the frame pulse signal, and a frequency dividing means for dividing the frequency of the frame pulse signal. , a reference burst that outputs a burst gate signal of a reference burst length to the modulation circuit, and outputs a carrier timing recovery code, a unique word, a control channel gate signal indicating a control channel part, and a symbol address signal of the control channel part. A combining means, a plurality of storage means for storing patterns and transmission orders of the control channel portions, a write control means for changing the contents of the storage means, and an output signal of the frequency division means to perform the time division multiplexing. a synchronization signal generating means for outputting a synchronization signal synchronized with a cycle that is an integral multiple (but not less than 1) of the connection frame cycle; selecting means for inputting the control channel gate signal and the symbol address signal and connecting another storage means to the write control means; and controlling the output of the one storage means by the output signal of the frequency division means. A pseudo-simulator comprising: a control means; and means for outputting the logical sum of the output of the one storage means controlled by the control means, the carrier timing, the reproduction code, and the unique word to the modulation circuit. Reference burst generator.