JPS61105654A - Address conversion control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an address translation control method in an information processing device, particularly an address translation table for storing and managing a plurality of address spaces, and a method for storing a part of this address translation table. An address that defines the correspondence when a part of the address translation table is stored in the translated address storage means when a translated address from the address space is translated into a physical address by an address translation mechanism equipped with a translated address storage means. Concerning conversion control method.

[Conventional technology]

When converting a translated address in one address space into a physical address using an address translation table that stores and manages multiple address spaces, address translation using conventional address translation control methods requires memory or registers that operate at high speed. An attempt was made to store a copy of a portion of the address space from an address translation table in a translated address storage means such as the above, in order to perform address translation at high speed.

In this conventional address translation control method, if memory is used as the translation address storage means, the amount of information that holds a copy of the address translation table increases, but it is difficult to execute address translation control at high speed. Met. Furthermore, when updating a copy of memory when a copy of a desired address space is not available, the algorithm is complex and the update process takes time, and there is a problem that the number of hardware is larger than when registers are used. .

On the other hand, when registers are used, the translated address storage means can be configured with a small amount of hardware and the address translation can be executed at high speed, but on the other hand, the amount of information required to hold a copy of the address translation table is Since the number of addresses is small, the number of exchanges of information between the address translation table and the register increases, which is disadvantageous in that it is difficult to perform address translation at high speed.

[Problem that the invention seeks to solve]

In conventional address translation control methods, as mentioned above, those that use memory as a means for storing translated addresses have the problem that it is difficult to perform address translation at high speed and requires a large amount of hardware. Although the system used had less hardware, it had the problem of not being able to perform address translation at high speed. As described above, in the conventional address translation control system, it is difficult to perform address translation at high speed with less hardware.

[Means for solving problems]

The present invention solves the above-mentioned problems in conventional address translation control methods, and provides a high-speed and efficient address translation control method using a minimum amount of hardware.
As a means for this purpose, an address translation mechanism that includes an address translation table that manages multiple address spaces and translation address storage means that stores a part of this address translation table is used to translate the translated address from the address space. In the address translation control method of
The address translation table includes an area for storing area identification information that instructs how to store the contents of the address conversion table in the converted address storage means, and furthermore, according to the instructions of this area identification information, the address conversion table is stored. It is configured to include means for storing a part of the translated address in the translated address storage means.

[For production]

The address translation table has, in addition to the access control information necessary for the address translation table and the physical address corresponding to the logical address in the address space, area identification information that instructs the response when storing in the translated address storage means. . The translated address storage means stores a part of the address translation table, and holds the logical address of the translated address from the address space and the corresponding physical address. When a translated address from an address space is input and the address space exists in the translated address storage means, address translation is performed based on the physical address stored in the translated address storage means. When the corresponding address space does not exist, the area portion of the address space corresponding to the address to be translated is stored in a predetermined area of the translated address storage means according to the instructions of the area identification information from the address conversion table, and based on this updated data. Address translation is performed. This allows high-speed address translation to be performed with a minimum amount of hardware.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings. 1st
Figure 2 is a block diagram showing the configuration of an embodiment of the present invention, Figure 2 is a block diagram showing the circuit configuration of an embodiment of the invention centering around the translated address storage means, and Figure 3 is an address conversion diagram of the present invention. FIG. 2 is a schematic explanatory diagram of an address conversion process using a control method.

First, an outline of the address translation process using the address translation control system of the present invention will be explained with reference to FIG.

In FIG. 3, AS (1 to n) are a plurality of address spaces used in the user state, and each address space has its own process area.

CT is an address translation table, and each address space AS
(1 to n) are managed separately. That is, the shared areas common to each address space are the shared program area CTCP and the shared data area CTCH, and the process areas of each address space are the user program area CTUP and the user data area CT.
It is divided and managed into each area of UD and user stack area CTUS.

As explained in detail in FIG. 1, the address translation table CT includes an address translation table C, which is a feature of the present invention.
An area identification information area CTDI is provided for storing area identification information that indicates the correspondence between the two when storing a part of T in the translated address storage section (CR). Note that each address space and the address conversion table form a logical space using logical addresses.

CR is a translation address storage area, and address translation table C
Corresponding to each area of T, shared programs, shared data,
It has user program, user data, and user stack areas, and an address conversion table CT is provided in these areas.
, along with their logical addresses (logical pages) and corresponding physical addresses (physical pages).

ps is a physical space that stores the physical addresses of the main storage device, and includes a kernel area PSKD, a shared area PSCD for each address space, and a user area PS used by each user.
UD, input/output control area I10, ROM area ROM where various control information is stored, memory area FM for display screen display
is provided.

Next, the address conversion process shown in FIG. 3 will be explained. As mentioned above, each address space AS (1 to n) is assigned to the shared program area CTC by the address translation table CT.
P, shared data area CTCD.

User program area CTUP, user data area CTUD
and a user stack area CTUS.

Part of the address space in this address translation table is
A copy is created in a fixed unit, for example, a page, and stored in the converted address storage section CR according to the instructions of the area identification information (this point will be explained in detail in FIG. 1 below).

When a translated address is input from one address space, the translated address storage unit CR creates a physical address corresponding to the translated address using it as reference information.

When the part of the address translation table corresponding to the address to be translated is not stored in the translated address storage section CR,
The original address conversion tape CT is addressed by the address to be converted, the entry portion corresponding to the address to be converted is read out, and the contents of the converted address storage section CR are updated. At this time, processing is performed to update and store a predetermined location in the translated address storage section CR according to the area identification information of the address translation table CT. Therefore, the update processing can be performed faster than any of the conventional methods described above, so that the overall address conversion processing can be speeded up.

FIG. 1 explains the structure of the address translation table CT and the translated address storage means CR, and the method of storing a part of the address translation table in the translated address storage means CR.

The address conversion table CT is a management table for arranging each address space in a physical space in fixed units (generally in page (4KB) units, hereinafter explained in page units).
As explained earlier, each address space is divided into a shared data area C.
It is divided and managed into TCD, shared program area CTCP, user stack area CTUS, user data area CTUD, and user program area CTUP area.

Each divided area stores entries CTE corresponding to the addresses to be translated from each address space, as shown in one example in the user program area CTUP. Each entry consists of, for example, 32 bits, and has an access control area CT that stores access control information.
A physical page area CTPP that stores the physical address corresponding to the logical page of the AC1 translated address and an area identification that stores area identification information indicating whether the entry is a program area, data area, stack area, shared area, etc. It has an area CTDI.

The area identification information has a 5-bit configuration, for example, and is "00000".
J is the program area, ro 0100J is the data area I, r
01000J is the data area ■, "01100" is the stack area, rl OOOOJ is the shared program area, rl 01
Area identification is performed so that 00J indicates the shared data area.

The translated address storage means CR includes a shared data area CRCD1, a shared program area CRCP, a user stack area CRUS, a user data area CRUD, and a user program area CRUP, corresponding to each area of the address conversion table. Each area has an access control area CRAC for storing access control information, a logical page area CRRP for storing the logical page of the translated address, and a physical page area CRPP for storing the physical page corresponding to this translated address. .

The translated address storage means CR is composed of, for example, a register in order to be able to perform address translation at high speed. Furthermore, if each area has at least one entry, that is, one address space bone in the address translation table CT, then address translation can be performed as explained in Figure 2 below. Therefore, the address translation mechanism including the translated address storage means CR can be configured with a minimum amount of hardware.

FIG. 2 is a block diagram showing a specific circuit configuration of the address translation control method of the present invention.

In FIG. 2, reference numeral 11 denotes a translated address input from the address space, which has a logical address configuration, and in this embodiment is configured by a logical page and an offset. 12
is an address translation boundary register (ATCR) in which an address value PGS serving as a boundary for address translation is stored. It is not necessary to perform address translation for all addresses to be translated from the address space, and there is no need to perform address translation for kernel area portions that are not related to the type of address space. The address (logical page) of this kernel area portion is set lower than the address (logical page) of the address space.

Therefore, by comparing the address translation boundary value PGS, which is the address value at the boundary between the two, and the page value of the translated address 11, it is possible to determine whether the translated address should undergo address translation. . 13 is a comparator, which compares the logical page value of the address to be converted 11 with the ATC
The address translation boundary value PGS of R12 is compared.

14A is the user program area CRUP of the conversion address storage means CR, 14B is the user data area CRUDIS
14C is user data area ffcRUD■, 140 is user stack area CRUS, 14E is shared program area CR
CP, 14F is a shared data area CRCD. Each area has an access control area CRAC, 8!, as described above. Management page area CRRP.

It has a physical page area CRPP. Access control area C
RAC has Invalid (1), Wr.
Its Protect (W), Accessed
(R) and Modified (C) access control information is stored.

15A, 15B, 15C, 15D, 15E, and 15F are comparator A, comparator B, comparator C1, comparator D1, comparator E, and comparator F, respectively, and the corresponding areas CRUP13A, C
RUD113B, CRUD1113C, CRUS13D
, CRCP13E, CRC:D13F and the logical page value of the converted address 11 are compared, and an output is generated only when they match.

16A to 16F are AND circuits that input the outputs of the corresponding comparators 15A to 15F and the negation of the r bit of the access control area CRAC, and 17A to 17F are the outputs of the corresponding AND circuits 16A to 16F and the negation of the r bit of the access control area CRAC. AND circuit whose output is input, 18 is AND circuit 17A to 17
an AND circuit whose inputs are the output of F and the output of comparator 13;
19 is an AND circuit whose inputs are the negation of the output of the comparator 13 and the page portion of the address to be converted 11, and 20A to 20F are inputs the outputs of the corresponding AND circuits 16A to 16F and the output of the W bit of the access control area CRAC. and circuit,
2LA to 21F are AND circuits which input the outputs of the corresponding AND circuits 20A to 20F and an inverted signal of a read/write signal (R/W), 22 to 24 are OR circuits, and 25 is an inverter.

Reference numeral 25 denotes a selector register, which inputs the area identification information read from the area identification area CTDI (see FIG. 1) of the address conversion table CT (not shown) and assigns logical pages and physical pages to the area of the corresponding conversion register storage CR. Perform storage.

26 is an address register in which the offset of the address to be translated 11 and the physical page corresponding to the logical page are written.

Next, the operation shown in FIG. 2 will be explained. When the converted address 11 is input from one of the address spaces not shown,
Comparator I3 stores the address translation boundary value PGS
and the logical page value of the address to be translated 11.

When the former is larger than the latter, it is determined that the address to be converted 11 is from the kernel area, and the conversion control signal T
Does not output C. Therefore, the logical page of the address to be translated 11 is written to the address register 26 via the AND circuit 19 and the OR circuit 22, and becomes a physical page. The offset from the address to be translated 11 is written in the address register 26, and a physical address in the kernel area is formed from these physical pages and offset values.

When the address conversion boundary value PGS is smaller than the logical page value of the address to be converted 11, the comparator 13 determines that the address to be converted 11 requires conversion and outputs the conversion control signal TC.

Therefore, the physical page output from any of the AND circuits 17A to 17F is determined by the AND circuit 18 and the OR circuit 2.
It will be written to the address register via 2.

On the other hand, the logical page of address 11 to be converted is
5A to one input terminal of comparator F15F. The other inputs of these comparators have the corresponding CRUD
14. Each logical page of A-CRCD 14E is added. Each comparator compares the two logical pages and generates a match output when they match. Assume now that the comparator is comparator D14D. The coincidence output from comparator D14D opens AND circuits 16D and 17D, and CRUS14
Physical page D is written to address register 26 via AND circuits 17D and 18 and OR circuit 22.

The ■ bit of the access control area CRAC is rOJ for the correct translated address 11.

Address register 26 forms the physical address corresponding to translated address 11 from the physical page written from CRUS 14D and the offset written from translated address 11.

By doing so, it is possible to convert the address to be translated from an arbitrary area of the address space (the user stack area in the above example) into a physical address of the corresponding physical space.

When there is no address space corresponding to the translated address 11 in the address space stored in the translated address storage means CR, no match output is generated from any of the comparators A15A to F15F. Therefore, no physical page is written to the address register 26.

At this time, the OR circuit 23 generates a fault signal. Upon receiving this fault signal, an addressing circuit (not shown) addresses the address translation table CT using the translated address 11 and reads out the physical page and area identification information of the entry from the entry corresponding to the translated address 11. The area identification information is supplied to the select register circuit 25, and on the other hand, the physical page forms update data together with the logical page of the translated address 11, and each area CRU of the translated address storage means CR
DI 4A NCRC DI Supplied to each logical page area and physical page area of 4F.

Upon receiving the area identification information, the selector register 25 selects an area in the translated address storage means CR to store the entry (CRUS14D in the embodiment), and selects the logical page and physical page area of that area (CRUS14D). Then, the physical page of the entry and the logical page of the translated address 11 are written in accordance with the update data, and their contents are updated.

As a result, a match output is generated by the comparator DI 5D, and a physical address corresponding to the translated address 11 is formed from the address register 26 as before.

This update operation is entirely performed by hardware, and the areas of the conversion address and address storage means to be updated are selected in advance based on the area identification information. It can be executed much faster than.

When a match output is generated from any of comparators A15A to F15F, the W (write protect) bit in the access control area, AND circuit 20 (A-F), AND circuit 21 (A-F), and OR A protection exception signal is generated by circuit 24 or the like to prevent erroneous updates.

As described above, whether or not a desired address space is stored in the translated address storage means CR, address translation for the corresponding physical address is executed at high speed.

In the above embodiment, one entry is stored from each area as part of the address translation table CT stored in the translation address storage means CR, but the present invention is limited to one entry. It also includes a case where a plurality of entries from each area of the address translation table CT are stored in the translated address storage means CR. In that case, the area identification information is stored in the corresponding translation address storage means CR.
This indicates the area and the entry number within that area.

〔Effect of the invention〕

As explained above, according to the present invention, each entry of each area of the address translation table has area identification information for the area in the translated address storage means in which they are stored. If a copy of the desired address space does not exist in the address translation table, the entry for the desired address space can be read from the address translation table to quickly update the predetermined area of the translated address storage means. Therefore, the entire address translation process can be executed at high speed. In addition, since the translated address storage means can be updated quickly, the amount of information for address translation stored in the translated address storage means can be kept to a minimum. An address translation mechanism including the following can be configured.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the address translation control method of the present invention, and FIG.
FIG. 3 is a block diagram illustrating a specific circuit configuration of the address translation control system of the present invention, and FIG. 3 is a diagram illustrating an address translation process using the address translation control system of the present invention. In the figure, 11 is the address to be translated, 12 is the address translation boundary register (ATCR), 13 is the comparator, and 14A is the user program area (CR) of the translated address storage means (CR).
UP), 14B is also the user data area I (CR
UDI), 14G is also user data area II (C
RUD■), 14D is also the user stack area (CRU
S), 14E is also the shared program area (CRCP)
, 14F is also the shared data area (CRCD), 15
A to 15F are comparators A to F, 16A to 16F,
17A to 17F, 18, 19, 20, and 21 are AND circuits, 22 to 24 are OR circuits, 25 is an inverter, and 26 is an address register, respectively. Further, CT indicates an address translation table, CTAC indicates an access control area, CTPP indicates a physical page area, and CTDI indicates an area identification area.

Claims (1)

[Claims] An address return control method when a translated address from an address space is translated by an address translation mechanism that includes an address translation table that manages multiple address spaces and a translated address storage means that stores a part of this address translation table. In the address conversion table, an area is provided for storing area identification information that instructs how to store the contents of the address conversion table in the converted address storage means, and further, the address conversion is performed according to the instructions of the area identification information. An address translation control system characterized in that means is provided for storing a part of the table in the translated address storage means.