JPS61114372U - - Google Patents
Info
- Publication number
- JPS61114372U JPS61114372U JP19946584U JP19946584U JPS61114372U JP S61114372 U JPS61114372 U JP S61114372U JP 19946584 U JP19946584 U JP 19946584U JP 19946584 U JP19946584 U JP 19946584U JP S61114372 U JPS61114372 U JP S61114372U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- trigger pulse
- outputs
- data pattern
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007704 transition Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Measurement Of Current Or Voltage (AREA)
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案を適用したロジツクアナライザ
の全体構成を示すブロツク図、第２図は第１図の
一動作例を表わすタイムチヤートである。
１……データ入力部、２……プローブ、３……
メモリ、４……表示回路、５……表示装置、６…
…設定部、７，８……コンパレータ、９，１０…
…トリガパルス、１１……データパターン。
FIG. 1 is a block diagram showing the overall configuration of a logic analyzer to which the present invention is applied, and FIG. 2 is a time chart showing an example of the operation of FIG. 1...Data input section, 2...Probe, 3...
Memory, 4...Display circuit, 5...Display device, 6...
...Setting section, 7, 8...Comparator, 9, 10...
...Trigger pulse, 11...Data pattern.
Claims (1)
パターンとして出力する入力部と、前記データパ
ターンとトリガパターンとを比較し、両者が一致
した時にトリガパルスを出力するコンパレータと
、前記トリガパルスを設定するための設定部と、
前記データパターンの時間に対する遷移を、逐次
記憶するメモリ部と、前記メモリ部の内容を表示
する表示回路及び表示器とを備えた装置に於いて
、 複数の前記コンパレータの中の一つがトリガパ
ルスを出力した時の現象を、そのつどメモリが記
憶更新する手段と、別のコンパレータがトリガパ
ルスを出力した時メモリの記憶更新を禁止してそ
の内容を表示する手段とからなることを特徴とす
るロジツクアナライザ。[Claims for Utility Model Registration] An input section that inputs a multi-channel digital signal and outputs it as a data pattern; a comparator that compares the data pattern and a trigger pattern and outputs a trigger pulse when the two match; a setting section for setting the trigger pulse;
In a device comprising a memory section that sequentially stores the transition of the data pattern over time, and a display circuit and a display that display the contents of the memory section, one of the plurality of comparators receives a trigger pulse. A logic system characterized by comprising means for a memory to update the memory each time a phenomenon is outputted, and a means for prohibiting the memory from updating and displaying the contents when another comparator outputs a trigger pulse. Tsuku Analyzer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19946584U JPS61114372U (en) | 1984-12-28 | 1984-12-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19946584U JPS61114372U (en) | 1984-12-28 | 1984-12-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61114372U true JPS61114372U (en) | 1986-07-19 |
Family
ID=30759414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19946584U Pending JPS61114372U (en) | 1984-12-28 | 1984-12-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61114372U (en) |
-
1984
- 1984-12-28 JP JP19946584U patent/JPS61114372U/ja active Pending
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