JPS61121154A - マルチプロセサシステムにおける制御方法 - Google Patents

マルチプロセサシステムにおける制御方法

Info

Publication number
JPS61121154A
JPS61121154A JP24250784A JP24250784A JPS61121154A JP S61121154 A JPS61121154 A JP S61121154A JP 24250784 A JP24250784 A JP 24250784A JP 24250784 A JP24250784 A JP 24250784A JP S61121154 A JPS61121154 A JP S61121154A
Authority
JP
Japan
Prior art keywords
program
shared memory
microprocessors
microprocessor
program module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24250784A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0140368B2 (th
Inventor
Teruo Goto
後藤　輝雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP24250784A priority Critical patent/JPS61121154A/ja
Publication of JPS61121154A publication Critical patent/JPS61121154A/ja
Publication of JPH0140368B2 publication Critical patent/JPH0140368B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP24250784A 1984-11-19 1984-11-19 マルチプロセサシステムにおける制御方法 Granted JPS61121154A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24250784A JPS61121154A (ja) 1984-11-19 1984-11-19 マルチプロセサシステムにおける制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24250784A JPS61121154A (ja) 1984-11-19 1984-11-19 マルチプロセサシステムにおける制御方法

Publications (2)

Publication Number Publication Date
JPS61121154A true JPS61121154A (ja) 1986-06-09
JPH0140368B2 JPH0140368B2 (th) 1989-08-28

Family

ID=17090128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24250784A Granted JPS61121154A (ja) 1984-11-19 1984-11-19 マルチプロセサシステムにおける制御方法

Country Status (1)

Country Link
JP (1) JPS61121154A (th)

Also Published As

Publication number Publication date
JPH0140368B2 (th) 1989-08-28

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