JPS6112385B2 - - Google Patents
Info
- Publication number
- JPS6112385B2 JPS6112385B2 JP52154821A JP15482177A JPS6112385B2 JP S6112385 B2 JPS6112385 B2 JP S6112385B2 JP 52154821 A JP52154821 A JP 52154821A JP 15482177 A JP15482177 A JP 15482177A JP S6112385 B2 JPS6112385 B2 JP S6112385B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- solder
- semiconductor
- semi
- solder paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかり、特に
半導体装置の外部リードの表面処理方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of surface treatment of external leads of a semiconductor device.
従来、半導体装置の外部リードの表面処理は、
その半導体装置の目的、用途などによつて種々の
方法が使用されてきた。従来の技術を大別すると
概ね以下の3方法である。まず第1の方法は、樹
脂封止型半導体装置、ガラス封止型半導体装置に
多用されているもので、半導体素子を封着後、外
部リード切断前に電解メツキを行うものである。
次に第2の方法は多層セラミツク容器を用いた半
導体装置や一部の樹脂封止型半導体装置に見られ
るように、容器又はリードフレームを製造する際
外部リードに電解メツキを行うものであり、半導
体素子組立後何らの表面処理を行なわず、そのメ
ツキ状態で製品となる。さらに第3の方法は場合
により適用されるもので外部リードを半田槽の中
に浸漬し、半田を付着させるものである。 Conventionally, the surface treatment of external leads of semiconductor devices was
Various methods have been used depending on the purpose and use of the semiconductor device. Conventional techniques can be broadly classified into the following three methods. The first method is often used for resin-sealed semiconductor devices and glass-sealed semiconductor devices, and involves performing electrolytic plating after sealing the semiconductor element and before cutting the external leads.
Next, the second method is to perform electrolytic plating on the external leads when manufacturing the container or lead frame, as seen in semiconductor devices using multilayer ceramic containers and some resin-sealed semiconductor devices. After the semiconductor elements are assembled, no surface treatment is performed, and the products are manufactured in the plated state. Furthermore, the third method, which is applied depending on the case, involves immersing the external lead in a solder bath to adhere the solder.
ところで、かような従来の方法については製品
のコストの点から次のような欠点があつた。すな
わち、第1の方法では半導体素子封止後電解メツ
キを行うため、電解メツキ製造ラインを作らなけ
ればらないが、その製造ラインは廃水処理装置に
対する投資や最近の厳しい環境規制における立地
場所の制限によつて、現実には不可能になりつつ
ある。又、たとえ可能であつても製品のコストは
その分上昇した。また第2の方法では、メツキを
行つた後半導体装置の組立工程を経るため、高温
で酸化し易いSn(スズ)などが使用できず、Au
(金)などの高価な金属を使用しなければなら
ず、やはり製品ストを下げることができなかつ
た。さらに第3の方法では確実に材料費は安くな
るが、半導体装置は個別になつているため大量生
産が難しく、また、半田槽の半田は刻一刻と不純
物が溶け込み品質が変るため、その品質を維持す
るには、半田槽の半田をその都度交換しなければ
ならずやはりコストを下げることは困難であつ
た。 However, such conventional methods have the following drawbacks in terms of product cost. In other words, in the first method, an electrolytic plating production line must be built to perform electrolytic plating after encapsulating the semiconductor element, but this production line requires investment in wastewater treatment equipment and restrictions on location due to recent strict environmental regulations. In reality, this is becoming impossible. Moreover, even if it were possible, the cost of the product would increase accordingly. In addition, in the second method, since the semiconductor device assembly process is performed after plating, materials such as Sn (tin), which easily oxidizes at high temperatures, cannot be used, and Au
However, expensive metals such as (gold) had to be used, and product costs could not be lowered. Furthermore, although the third method definitely reduces material costs, it is difficult to mass-produce semiconductor devices because they are made individually, and the quality of the solder in the solder bath changes from moment to moment as impurities melt into it. To maintain this, the solder in the solder tank must be replaced each time, making it difficult to reduce costs.
本発明はかような欠点をなくし、安価で品質の
安定した半導体装置を提供することを目的とす
る。 It is an object of the present invention to eliminate such drawbacks and provide a semiconductor device that is inexpensive and of stable quality.
本発明は、半導体装置の外部リードに半田ペー
ストを塗布し、焼成したことを特徴とする。 The present invention is characterized in that a solder paste is applied to the external leads of a semiconductor device and then baked.
以下図面を用いて本発明の実施例を説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図A,B,Cは従来の半田槽を用いて表面
処理を行う半導体装置の斜視図である。例えば長
い金属薄板例えばコバールをプレスして各一個の
半導体装置となるパターンを連続して形成したリ
ードフレーム1に公知の方法で半導体素子を接続
し、金属細線を所定の箇所に配線した組立体をエ
ポキシ樹脂2で封止した半導体装置半製品3を形
成して(第1図A)、この各半導体装置半製品3
を個別にプレスで分離し、さらに外部リード4を
所定のDIP形状でプレスで形成する。その後各半
導体装置半製品3の樹脂表面に捺印を行ない乾燥
させる(第1図B)。かようにしてほぼ最終形状
にされた状態で、外部リード4に適当なフラツク
スをつけ、例えばPb―Sn共晶ハンダを入れた半
田槽に浸す。そして最終的には外部リード4には
半田槽5が設けらた構造(第1図C)となり出荷
される。 1A, B, and C are perspective views of a semiconductor device whose surface is treated using a conventional solder bath. For example, a semiconductor element is connected by a known method to a lead frame 1 in which a long thin metal plate such as Kovar is pressed to form a continuous pattern for each semiconductor device, and thin metal wires are wired at predetermined locations to form an assembly. A semiconductor device semi-finished product 3 sealed with an epoxy resin 2 is formed (FIG. 1A), and each semiconductor device semi-finished product 3 is
are individually separated using a press, and further, the external leads 4 are formed into a predetermined DIP shape using a press. Thereafter, a mark is applied to the resin surface of each semiconductor device semi-finished product 3 and dried (FIG. 1B). With the external lead 4 thus formed into almost the final shape, a suitable flux is applied to the external lead 4, and the lead is immersed in a solder bath containing, for example, Pb--Sn eutectic solder. Finally, the structure in which the external lead 4 is provided with the solder bath 5 (FIG. 1C) is shipped.
ところでかような従来の方法では、半導体装置
を個別に分離しないと半田浸しすることができず
大量生産的でなく、また半田槽の不純物量の管理
や、半田の交換などで工数や費用をかけるため結
果として製品コストの上昇をもたらしていた。 By the way, with such conventional methods, semiconductor devices cannot be dipped into solder unless they are separated individually, making it difficult to mass-produce, and also requiring man-hours and costs to manage the amount of impurities in the solder bath and replace solder. This resulted in an increase in product costs.
第2図A,B,Cは本発明による半導体装置の
斜視図である。例えば従来公知のコバール等より
なるリードフレーム1にこれまた公知の方法で半
導体素子等を封止したエポキシ樹脂2を構成(第
2図A)した半導体半製品3に対しまずコバール
表面を清浄にするためトリクレンなどによる溶剤
洗浄あるいはノニポールなどによるアルカリ洗浄
を行い、さらにHClなどで酸洗浄を加える。その
後、外部リード4に半田ペースト6をスクリーン
印刷法で形成する(第2図B)。この半田ペース
ト6は、例えば350メツシユ程度の細粒Pb―Sn
(38%)半田を約70%にその他樹脂、塩化アンモ
ン、軟質石油、ワツクスなどを加えたもので市販
されている。 2A, B, and C are perspective views of a semiconductor device according to the present invention. For example, for a semi-conductor semi-finished product 3 comprising a lead frame 1 made of conventionally known Kovar or the like and an epoxy resin 2 sealed with a semiconductor element etc. by a known method (FIG. 2A), the Kovar surface is first cleaned. Therefore, perform solvent cleaning such as Triclean or alkaline cleaning such as Nonipol, and then add acid cleaning such as HCl. Thereafter, solder paste 6 is formed on the external leads 4 by screen printing (FIG. 2B). This solder paste 6 is made of fine particles of Pb-Sn of about 350 mesh, for example.
(38%) It is commercially available with approximately 70% solder and other resins, ammonium chloride, soft petroleum, wax, etc.
さて半田ペーストを塗布した後、約170℃前後
で焼成し、完全に接着させる。この焼成は通常の
恒温槽あるいは、電気炉、ベルト(連続)炉で可
能である。さらに、半導体装置半製品3の樹脂表
面に捺印を行い乾燥し、各半導体半製品3をリー
ドフレームより分離し、外部リードを成形する
(第2図C)。 Now, after applying the solder paste, it is baked at around 170℃ to ensure complete adhesion. This firing can be performed in a regular thermostatic oven, electric furnace, or belt (continuous) furnace. Furthermore, a mark is applied to the resin surface of the semiconductor device semi-finished products 3 and dried, each semiconductor semi-finished product 3 is separated from the lead frame, and external leads are formed (FIG. 2C).
かようにして、本発明の半導体装置の製造方法
は、半田ペーストを塗布し焼成するため従来に比
して、大量生産が出き、また安価に作ることがで
きる。 In this way, the method for manufacturing a semiconductor device of the present invention involves applying a solder paste and baking it, so that it can be mass-produced and manufactured at a lower cost than in the past.
また、例えば捺印工程は半田ペースト塗布前に
行い塗布後の焼成で捺印乾燥を兼ねても良いため
規定することはない。 Further, for example, the stamping process may be performed before applying the solder paste and the baking after application may also serve as the sealing drying, so there is no stipulation.
第1図A至第1図Cは従来技術による半導体装
置の製造方法を工程順に示した斜視図である。第
2図A至第2図Cは本発明の一実施例を工程順に
示した斜視図である。
尚、図において、1……リードフレーム、2…
…樹脂、3……半導体装置半製品、4……外部リ
ード、5……半田層、6……半田ペーストであ
る。
FIGS. 1A to 1C are perspective views showing a conventional method for manufacturing a semiconductor device in the order of steps. FIGS. 2A to 2C are perspective views showing an embodiment of the present invention in the order of steps. In the figure, 1...lead frame, 2...
...Resin, 3...Semiconductor device semi-finished product, 4...External lead, 5...Solder layer, 6...Solder paste.
Claims (1)
田ペースト層を形成する工程と、該半田ペースト
層を焼成する工程とを少くとも具備することを特
徴とした半導体装置の製造方法。1. A method for manufacturing a semiconductor device, comprising at least the steps of forming a solder paste layer on at least a portion of an external lead of the semiconductor device, and firing the solder paste layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15482177A JPS5486275A (en) | 1977-12-21 | 1977-12-21 | Manufacture of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15482177A JPS5486275A (en) | 1977-12-21 | 1977-12-21 | Manufacture of semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5486275A JPS5486275A (en) | 1979-07-09 |
| JPS6112385B2 true JPS6112385B2 (en) | 1986-04-08 |
Family
ID=15592600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15482177A Granted JPS5486275A (en) | 1977-12-21 | 1977-12-21 | Manufacture of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5486275A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61267355A (en) * | 1985-05-21 | 1986-11-26 | Fuji Plant Kogyo Kk | Cladding process at semiconductor package assembly process |
| JPS63142841A (en) * | 1986-12-05 | 1988-06-15 | Fuji Plant Kogyo Kk | Method of solder sheathing treating to lead frame |
| JPS63148669A (en) * | 1986-12-12 | 1988-06-21 | Fuji Plant Kogyo Kk | Solder cladding for lead frame |
-
1977
- 1977-12-21 JP JP15482177A patent/JPS5486275A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5486275A (en) | 1979-07-09 |
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