JPS6113406B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an AGC circuit for a radio receiver, and particularly provides an AGC circuit that can effectively apply AGC to the first stage of an intermediate frequency amplification stage and a frequency conversion stage, and is suitable for integrated circuits. The purpose is to

Generally, in AM radio receivers, the AGC circuit is configured to change the gain of the first stage of the frequency conversion circuit and intermediate frequency amplification circuit, and the characteristics of the received signal level versus detection output level (AGC
characteristics).

In designing the above AGC circuit, the gain of the first stage of the intermediate frequency amplification circuit mainly decreases when the received signal level is medium as shown in Figure 2 (b) (the gain of the frequency conversion circuit is the same as that of (a) at weak input). ), and the gain of the first stage of the frequency conversion circuit and the intermediate frequency amplification circuit is set so as to both decrease at a place where the received signal level is high as shown in FIG. 2C. This is to ensure good S/N characteristics at each received signal level. For example, if an AGC operation is performed to reduce the gain of the frequency conversion circuit at a medium received signal level, (b) This leads to deterioration of the S/N characteristics at the received signal level.

According to the present invention, as the received signal level increases, the AGC is activated at a timing in which the gain is sequentially decreased from the first stage of the intermediate frequency amplification circuit to the frequency conversion circuit in order to obtain the optimum S/N characteristic according to each level. The invention provides an AGC circuit that can operate, and the present invention will be described below with reference to drawings of embodiments.

FIG. 1 shows an embodiment in which the present invention is applied to a MW1 band radio receiver, and in the figure,
is a frequency conversion circuit, is a local oscillation circuit, is a constant voltage circuit for providing bias to the above frequency conversion circuit and local oscillation circuit, is an intermediate frequency amplification circuit, V is an AM detection circuit, is an AGC amplifier, is the above intermediate frequency amplification Circuit, AM detection circuit V and AGC
This is a constant voltage circuit that provides bias to the amplifier.

Here, the frequency conversion circuit includes a first differential amplifier in which the emitters of the first transistor _Q5 and the second transistor _Q9 are coupled to each other, and a collector is coupled to the emitters of the first differential amplifier. a third transistor _Q10 whose emitter is grounded via a first resistor _R4 , and a fourth transistor _Q3 connected to the collector of the first transistor _Q5 .
a second differential amplifier in which the emitter of a sixth transistor Q7 and the emitter of a _seventh transistor _Q8 are coupled to each other, and the emitter of a sixth transistor _Q7 and the emitter of a seventh transistor _Q8 are connected to the collector of the second transistor Q9; A third differential amplifier is provided in which the differential amplifiers are coupled together. The emitters of the transistors Q ₃ , Q ₄ , Q ₇ , Q ₈ constituting the second and third differential amplifiers are coupled to the power supply via resistors R ₅ and R ₆ , and the fourth transistor Q ₃ collector and the 6th
The collector and base of the transistor Q ₇ and the base of the fifth transistor Q ₄ are coupled to a power supply, and the collector of the fifth transistor Q ₄ and the collector of the seventh transistor Q ₈ are coupled to each other to generate a voltage of 455 KHz. is coupled to the power supply via an IFT (first coil) tuned to Further, the base of the fourth transistor Q ₃ and the base of the seventh transistor Q ₈ are coupled to each other and to a power source via the secondary winding of the antenna coil 2. The capacitor 1 constitutes a tuning circuit together with the antenna coil 2, and the input signal is directly injected from the secondary winding of the antenna coil 2 into the bases of transistors Q ₃ and Q ₈ which are the input stage of the frequency conversion circuit. Transistors Q ₁ , Q ₂ , and resistor R ₁ are for providing base bias of transistor Q ₅ , and transistors Q ₁₃ , Q ₁₄ , and resistor R ₈ are for providing bias to the base of transistor Q ₉ . At the same time, a local oscillation signal is injected into the base of transistor _Q9 via transistor _Q13 . The transistor _Q10 is a constant current stage for supplying current to the first, second, and third differential amplifiers, and its base is biased by a diode _D5 and a resistor _R7 . R ₄ is its emitter resistance. Therefore, the transistors Q ₃ , Q ₄ , Q ₇ ,
Q ₈ , Q ₅ , and Q ₉ constitute a balanced frequency conversion circuit, in which the input signal and local oscillation signal are mixed.
An intermediate frequency signal is extracted by IFT3 tuned to 455KHz.

The local oscillation circuit is composed of transistors Q ₁₅ and Q ₁₆ , and its oscillation frequency is determined by the oscillation coil 7.
is determined by a capacitor 8 communicating with the capacitor 1 and having a variable capacitance. Transistor Q ₁₇ is a constant current stage of the transistors Q ₁₅ and Q ₁₆ , and the current is determined by resistor R ₁₂ . resistance
R ₁₁ , R ₉ , R ₁₀ are the above transistors Q ₁₅ , Q ₁₆ respectively
The oscillation signal is applied to the resistor.
R ₁₀ , the above transistor through transistor Q ₁₃
It is injected into the base of _Q9 .

The constant voltage circuit consists of transistors Q ₁₈ , Q ₁₉ , Q ₂₀ ,
It is composed of diodes D ₁ , D ₂ and resistors R ₁₅ , R ₁₃ , and R ₁₄ , and a bias is applied to the bases of the transistors Q ₂ , Q ₁₄ , and Q ₁₇ from the voltage dividing point of the resistors R ₁₃ and R ₁₄ . ing. Further, the collector of the transistor Q ₁₉ is coupled to the base of the transistor Q ₁₁ to form a current mirror, and biases the diode D ₅ and the resistor R ₇ with a constant current.

On the other hand, the intermediate frequency signal extracted by the IFT 3 is input to an intermediate frequency amplification circuit via a ceramic filter 4.

The intermediate frequency amplification circuit consists of transistors Q ₂₅ , Q ₂₆ , Q ₂₇ , Q ₂₈ , Q ₃₀ , Q ₃₁ , load resistances R ₁₈ , R ₁₉ , R ₂₁ , R ₂₂ , R ₂₄ , R ₂₅ , and load resistances that constitute a differential amplifier. _R26 , and current is supplied to each differential amplifier by constant current transistors _Q24 , _Q29 , and _Q32, respectively. The current is determined by resistors R ₂₀ , R ₂₃ and R ₂₇ . Transistor Q ₂₃ is the detection output,
In other words, the base potential of the transistor is controlled according to the magnitude of the input signal.
Configure a differential amplifier with Q ₂₄ , and use the transistor
It constitutes an AGC amplifier that changes the current flowing through _Q24 . The collector current of the transistor Q ₂₃ is guided to a current mirror composed of transistors Q ₂₂ and Q ₂₁ , and a current equal to the magnitude of the current is passed from the collector of the transistor Q ₂₁ to the resistor R _2.
and generates a voltage across it. and,
The generated voltage biases the base of the transistor Q ₆ and causes a current determined by the resistor R ₃ to flow, while removing the base bias of the transistor Q ₁₀ and converting the transistors Q ₃ , Q ₄ , Q ₇ , Q ₈ , Q _Five ,
Reduces the current of the balanced frequency conversion circuit composed of _Q6 and its amplification degree. At that time, the emitters of the transistors Q ₃ , Q ₄ , Q ₇ , and Q ₈ that constitute the second and third differential amplifiers are pulled up to the power supply line by the resistors R ₅ and R ₆ , and the emitters of the transistors
Q ₃ , Q ₄ , Q ₇ , and Q ₈ are close to cutoff. Also resistance
R ₃₄ , R ₃₅ , capacitors C ₂ , C ₃ connect the collectors of transistors Q ₃₀ , Q ₃₁ which constitute the final stage differential amplifier of the intermediate frequency amplifier circuit to transistors Q ₂₆ , Q ₂₇ which constitute the first stage differential amplifier. An AC removal filter is configured to apply DC feedback to the base of the The intermediate frequency signal amplified by the intermediate frequency amplifier circuit is guided to the AM detection circuit V composed of transistors Q ₃₃ and Q ₃₄ , where the intermediate frequency signal is detected and also composed of resistor R ₃₆ and capacitors C ₄ and C ₅ . The signal is output from terminal 6 as a low frequency output signal via an integrating circuit.

Transistor Q ₃₆ and resistor R ₂₈ are each transistor
A constant current stage is configured to supply current to Q ₃₃ and Q ₃₄ .

AGC amplifier consists of transistors Q ₃₆ , Q ₃₇ , Q ₃₈ ,
Q ₃₉ , resistors R ₂₉ , R ₃₀ , R ₃₁ , and capacitor C ₄ , and a bias voltage is applied to the base of the transistor Q ₃₆ from the emitters of the transistors Q ₃₃ and Q ₃₄ . Also, the above transistor
A bias voltage is applied to the base of _Q37 from the voltage dividing point of resistors _R25 and _R26 through the emitter of the transistor _Q38 . Then, by adjusting the voltage dividing points of resistors R ₂₅ and R ₂₆ , the base voltage of transistor Q ₃₇ is set so that the current determined by resistor R ₂₉ flows to transistor Q ₃₆ . Therefore, when the received input signal becomes larger, the base bias of the transistor _Q36 becomes shallower due to the detection output corresponding to the input signal, and the current determined by the resistor R29 becomes the same as the current determined by the resistor _R29 . The current flows into the transistor _Q37 , a voltage is generated across the resistor _R30 , and the alternating current component is removed by the capacitor _C4 . Then, the DC voltage applies a bias to the base of the transistor Q ₂₃ , causing current to flow through the transistor Q ₂₃ via the resistor R ₂₀ , while decreasing the current flowing to the transistor Q ₂₄ , thereby reducing the current flowing through the transistor Q ₂₅ and Q. AGC is applied by lowering the gain of the differential amplifier consisting of ₂₆ . _The constant voltage circuit is composed of transistors Q ₄₄ , Q ₄₁ , Q ₄₂ , diodes D ₃ , D ₄ , and resistors _{R 32 ,} R ₃₁ , R ₃₃ .
Bias is given to the bases of Q ₂₄ , Q ₂₉ , Q ₃₂ , Q ₃₅ , and Q ₃₉ .

The capacitor C ₁ and the resistor R ₁₆ are decoupled springs inserted into the power supply line, and the terminal 5 is a power supply terminal for supplying power to operate the entire circuit.

As described above, according to the present invention, as the received signal level increases, the optimum S/S/
In order to obtain the N characteristic, the AGC operation can be performed at a timing such that the gain sequentially decreases from the first stage of the intermediate frequency amplification circuit to the frequency conversion circuit, and has the advantage that the timing of the AGC operation can be easily set. That is, the AGC DC voltage from the detection circuit is applied to the base of the 12th transistor, but since the 12th transistor constitutes the fifth differential amplifier, the collector current ( At the same time as the emitter current) flows, the 11th
The collector current of the transistor decreases, and the gain of the fourth differential amplifier decreases. On the other hand, the collector current of the 12th transistor applies a base bias to the 8th transistor via a current mirror composed of the 12th and 13th transistors, diverts the current of the diode biased to the constant current source, and divides the current of the diode biased by the constant current source. In order to lower the potential of the diode and lower the base bias of the third transistor, the gain of the frequency conversion circuit constituted by the first, second, and third differential amplifiers is lowered. By configuring the AGC circuit as described above, it is possible to inevitably set the timing at which the gain of the frequency conversion circuit is reduced from the first stage of the intermediate frequency amplification circuit as the received signal level increases. In both cases, the gain of the frequency conversion circuit decreases before the gain of the intermediate frequency amplification circuit, and the S/N ratio at the intermediate input level of the received signal does not deteriorate. In the conventional design of a radio receiver, it has been difficult to determine the timing of the AGC operation, but by adopting the circuit configuration of the present invention, an AGC circuit with good S/N characteristics can be easily realized. Moreover, according to the present invention, the circuit configuration is such that differential amplifiers are directly connected in multiple stages, so it is very suitable for integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment based on the present invention, and FIG. 2 is an AGC characteristic diagram of an AM radio receiver. ...Frequency conversion circuit, ...Local oscillation circuit,
...Intermediate frequency amplifier circuit, ...AM detection circuit,
...AGC amplifier, ...constant voltage circuit.

Claims (1)

[Claims] 1 Comprising a frequency converter that mixes an input signal and a local oscillation signal and outputs an intermediate frequency signal, and an intermediate frequency amplifier to which the intermediate frequency signal from the frequency converter is added, the signal obtained from the intermediate frequency amplifier In the AGC circuit configured to control the gains of the intermediate frequency amplifier and the frequency converter based on the DC potential corresponding to the input signal detected, the frequency converter includes a first transistor and a second transistor. a first differential amplifier whose emitters are coupled to each other; and a third transistor whose collector is coupled to the emitter of the transistor constituting the first differential amplifier and whose emitter is grounded via a first resistor. and a second differential amplifier in which the collector of the first transistor is coupled to a connection point where the emitters of the fourth transistor and the emitter of the fifth transistor are connected to each other; a third differential amplifier connected to a connection point where the emitters of the sixth transistor and the emitter of the seventh transistor are connected to each other, and constitute the second differential amplifier and the third differential amplifier. The emitter of each of the transistors is coupled to a first power supply via second and third resistors, and is connected to the collector of the fourth transistor, the collector and base of the sixth transistor, and the base of the fifth transistor. is coupled to a first power supply, the collector of the fifth transistor and the collector of the seventh transistor are coupled to each other, and the coupling point is coupled to the first power supply via a first coil, and the The base of the fourth transistor and the base of the seventh transistor are coupled to each other, the coupling point is coupled to the first power supply via the second coil, and the base of the third transistor is connected to the base of the eighth transistor. and an anode of a diode biased by a constant current source, so that an input signal is applied from the second coil and an output signal is obtained from the first coil, and the collector is connected to the first transistor. configured to give a local oscillation signal from the base of at least one of the second transistors,
On the other hand, the intermediate frequency amplifier includes a fourth differential amplifier in which an output signal obtained from the first coil constituting the frequency converter is applied to at least one transistor, and a fourth differential amplifier constituting the fourth differential amplifier. 9. an eleventh transistor whose collector is connected to the connection point of each emitter of the tenth transistor, and the emitter of the twelfth transistor is connected to the emitter of the eleventh transistor to form a fifth transistor. The collector of one of the transistors is connected to the collector of the twelfth transistor to form a differential amplifier, and a current mirror circuit consisting of thirteenth and fourteenth transistors whose emitters are coupled to a second power supply is connected to the collector of the twelfth transistor. The collector of the other transistor constituting the current mirror circuit is connected to the base of the eighth transistor provided in the frequency converter, and the configuration is configured such that a DC potential corresponding to the input signal is applied to the base of the twelfth transistor. The AGC circuit is characterized by: