JPS6113633B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image information processing device, and in particular to a CPU.
The present invention relates to an image information processing device that can directly access a large-capacity external memory connected to a separate bus line from the computer.

Conventionally, as memories for storing image information, media such as magnetic disks 4 and magnetic tapes as shown in Figure 1, which have a low storage cost per bit and can store large amounts of information, have been used. However, the memory access time is long, and data reading and
Since writing takes time, real-time processing is not possible.

IC memory is a storage medium for processing image information in real time, but using a large number of IC memories reduces reliability and increases cost, making it impractical.

However, with the remarkable development of semiconductor technology, it is expected that it will not be long before the emergence of highly reliable, high packaging density, and low-cost IC memories.

By the way, such a large and fast RAM
appears, in a single-bus processing device,
Even if a high-speed, large-capacity RAM is connected to a bus together with a CPU, main memory, input/output device, etc., high-speed transfer of image information cannot be achieved. That is, conventionally,
In the main memory of mini-computer class,
Since the capacity is about 512K bytes, 18 address lines are sufficient to access it, whereas image information memory has an extremely large capacity of about 9M bytes, so it is difficult to access it. This would require 25 address lines and require changes to the traditional system architecture.

Therefore, the present inventor filed a separate application on the same date as the present application entitled "Image information processing device" (Japanese Patent Laid-Open No. 56-118164).
proposed a processing device with the configuration shown in the specification of No. As shown in Figure 1, this means that CPU1,
In addition to the CPU bus line 20 shared by the main storage device 2, magnetic disk device 4, CRT display 5, etc., a large-capacity high-speed RAM 8 for image information,
A new external memory bus line 30 is installed to be shared by the scanner 6, plotter 7, etc. for image information input/output, and both bus lines 20 and 30 are connected to the bus line 30.
They are coupled via a converter 10.

The external memory bus line 30 allows data lines, address lines, and control lines to be set appropriately according to the amount of information transferred, so it can perform DMA (direct memory access) without being affected by the configuration of the CPU bus line 20. ) By adding this function to the input/output interface 3, high-speed transfer of image information is possible.

With the configuration shown in FIG. 1, image information can be processed in real time using a large-capacity high-speed memory, and there is no loss of compatibility with conventional processing devices in terms of hardware and software.

However, the external memory bus line 30 in Figure 1
The information transfer between the input/output devices 6, 7 connected to the external memory 8 and the external memory 8 can be performed in real time, whereas the information transfer between the CPU bus line 20 and the external memory bus line 30 can be performed in real time. Information transfer is difficult to access due to the different configurations of bus lines, and requires conversion of addresses, data, etc. in the bus converter 10.
Unable to process in time.

SUMMARY OF THE INVENTION In order to solve these problems, it is an object of the present invention to make it possible to directly access an external memory connected to a separate bus line from a CPU, thereby eliminating the need for conventional processing devices, hardware, and software. An object of the present invention is to provide an image information processing device that can control a high-speed memory for image information while maintaining compatibility.

The image information processing device of the present invention includes a first bus line shared by a CPU and a main memory, and an external memory connected to the first bus line via a bus converter and for image information. and an image information processing device having a second bus line shared by the image information input/output device, wherein an arbitrarily divided area of the external memory is provided as a mapped external memory area in the main storage device, and A memory mapping register for distinguishing between divided external memory areas is provided in the bus converter, and the address of the mapped external memory area and the contents of the memory mapping register are used to directly connect external memory from the CPU. It is characterized by accessing memory.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing the correspondence between a mapped external memory area provided in the main storage device of the present invention and divided areas of the external memory.

FIG. 2 shows a case where the capacity of the external memory 8 is 1M words, the number of divided banks is 250, and the divided unit area is 4K words.

In addition to storing the program of the CPU 1 in the main memory device 2 having a capacity of 32K words,
If image information could also be stored, there would be no need for the CPU 1 to access the external memory 8 connected to a separate bus line 30.

In the present invention, the program for the CPU 1 is stored in the 0 to 28K word area of the main storage device 2,
An area of the external memory 8 is reserved in an area of 28 to 32K words. That is, although image information is not stored in the main memory 2, only an area is allocated for image information, and when the CPU 1 accesses 28 to 32K words, it is assumed that the external memory 8 has been accessed.

On the other hand, the external memory 8 is divided into 250 banks of the same size, BK0 to
It becomes a set of 249.

CPU1 has 28 to 32K words (4K
When the (word) area is accessed with an arbitrary address, the same address in 250 banks BK0 to BK249 of the external memory 8 is accessed in common. Therefore, if one of the 250 banks can be identified, it means that one address in the external memory 8 has been accessed. Therefore, in the present invention, a mapping register is provided to identify the bank, and at the same time when the mapped external memory area MPM of the main storage device 2 is accessed from the CPU 1, a value that specifies one of the 250 in the mapping register is provided. Set.

Thereby, the CPU 1 can control the external memory 8 as if it were in the main storage device 2.

FIG. 3 is a detailed block diagram of the bus controller of FIG. 1.

CPU bus line 20 and external memory bus
A bus line driver/receiver 11 is connected to each line 30 to transmit and receive signals. Both bus line drivers/receivers 1
1, a data control circuit 12, an address decoder 13, a memory mapping register 1
4, an interrupt control circuit 15 and a control status register 16 are connected.

The data control circuit 12 consists of a buffer memory and a register for parallel/serial conversion, and for example, when a 16-bit data line is used as the CPU bus line 20 and a 32-bit data line is used as the external memory bus line 30. temporarily stores data in a buffer memory, divides it into two times, or combines the two times into one, and outputs the data to each data line.

When the CPU 1 accesses the mapped external memory MPM area of the main storage device 2, the address decoder 13 inputs and decodes the address.

Memory mapping register 14
1 sets a value specifying one of 250 banks.

When interrupting the CPU 1 from a device connected to the external memory bus line 30, the interrupt control circuit 15 receives an interrupt request signal via a control line or a data line, and notifies the CPU 1 of the interrupt request signal.

When the CPU 1 receives an interrupt request, it switches to the PSW (program status word) of the corresponding level and branches to the interrupt analysis routine.

The control status register 16 is
It displays the status of the CPU bus line 20 and external memory bus line 30. for example,
When the external memory 8 is transferring data by DMA, the CPU 1 cannot access the external memory 8, so the CPU 1 refers to the control status register 16 and performs access after the indication that the transfer is in progress is canceled. In the same way, when both the information input/output devices 6 and 7 want to transfer data by DMA, they refer to this register 16 and transfer the data to the CPU 1.
After confirming that no transfer is in progress between the external memory 8 and the external memory 8, start DMA transfer.

FIG. 4 shows the bit configuration of the address register and mapping register of the present invention.

In FIG. 4, the mapped external memory area of the main storage device 2 is 4K words, and 1 word is 2K words.
Since it is a byte, this capacity is 8K bytes. To access an 8K byte area, a 13-bit address register is required and
An 8-bit mapping register is required to identify the 250 banks. Therefore, address register ADRG shown in FIG. 4a and mapping register MPRG shown in FIG. 4b are both 16-bit registers, of which address register ADRG is 13 bits and mapping register MPRG is It is sufficient to use 8 bits of . The extra bits are reserved for when the external memory 8 and main memory 2 are replaced with ones of different capacity.

5 and 6 are diagrams showing the connections and configurations of the address register and mapping register in FIG. 4.

In order to access the mapped external memory area of the main memory device 2, the CPU 1 sets an address in the address register ADRG via the address line, and also sets an address in the mapping register ADRG via the data line to specify the bank of the external memory 8. MPRG
Set the bank designation number to . These addresses and bank designation numbers are all transferred to external memory 8 via address lines on external memory bus line 30. For example, CPU bus line 2
If an 18-bit address line is installed at 0 and a 25-bit address line is installed at external memory bus line 30, when accessing the mapped external memory area with 13 bits, the remaining 5 address lines are connected to the address line.
Since there are only 8 bits and the 5-bit bank designation number to be set in the mapping register MPRG cannot be sent out via the remaining address lines, 8-bit data lines are used to send out. One external memory bus line 30 uses a 25-bit address line to address the 13th and 8th bits of both registers.
The contents of the bits are simultaneously transferred to the external memory 8.

Therefore, as shown in Figure 5, the address
The register 17 is connected between each address line ADL of the CPU bus line 20 and the external memory bus line 30, and the mapping register 14 is connected between the data line DTL and the address line ADL. Note that the address register 1 shown in FIG.
7 is actually the external memory bus line 30
The address line ADL is not directly connected to the address line ADL of the address line ADL, but is connected to the address line ADL via an address decoder 13 (see FIG. 3).

FIG. 6 is a configuration diagram of an address register and a mapping register showing another embodiment of the present invention.

When the CPU bus line 20 is provided with an 18-bit address line and the external memory 8 has a capacity of 4 Mbytes, the main memory 2 is
It is divided into a 512K byte program area and a 512K byte map external memory area, and the external memory 8 is divided into eight banks of 512K bytes each.

As shown in FIG. 6, an 18-bit address register 17 allows access to the program area of the main memory 2 and a mapped external memory area, and a 3-bit mapping register 14 allows access to eight banks. can be specified.

As explained above, according to the present invention, the CPU
Using the address line and data line of the bus line,
By setting the address of the divided area of external memory and the contents that identify the divided area in the address register and mapping register,
It is now possible to directly access external memory from the CPU, thus maintaining compatibility between conventional hardware and software.
High-speed image information memory can be controlled in real time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image information processing device that is the premise of the present invention, FIG. 2 is a correspondence diagram of a main storage device and external memory showing an embodiment of the present invention, and FIG. 3 is a diagram showing an embodiment of the present invention. Bus controller block diagram,
FIG. 4 is a bit configuration diagram of the address register and mapping register of the present invention, and FIGS.
The figures are a connection diagram and a configuration diagram of an address register and a mapping register, respectively, showing other embodiments of the present invention. 1: CPU, 2: Main memory, 3: Input/output interface, 4: Magnetic disk, 5: CRT display, 6: Scanner, 7: Printer, 8:
External memory, 9: External memory controller, 1
0: Bus converter, 11: Bus line driver receiver, 12: Data control circuit, 1
3: Address decoder, 14: Memory mapping register, 15: Interrupt control circuit, 16:
Control status register, 17: Address register.

Claims (1)

[Claims] 1 A first bus line shared by the CPU and main memory, and connected to the first bus line via a bus converter and shared by an external memory for image information and an image information input/output device. In the image information processing device, an arbitrarily divided area of the external memory is provided in the main storage device as a mapped external memory area, and the divided external memory area is provided as a mapped external memory area. A memory mapping register for differentiation is provided in the bus converter, and the CPU directly accesses the external memory based on the address of the mapped external memory area and the contents of the memory mapping register. Image information processing device.