JPS61140586U - - Google Patents
Info
- Publication number
- JPS61140586U JPS61140586U JP2333585U JP2333585U JPS61140586U JP S61140586 U JPS61140586 U JP S61140586U JP 2333585 U JP2333585 U JP 2333585U JP 2333585 U JP2333585 U JP 2333585U JP S61140586 U JPS61140586 U JP S61140586U
- Authority
- JP
- Japan
- Prior art keywords
- collective
- terminal
- circuit board
- printed circuit
- light emitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004088 simulation Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Locating Faults (AREA)
Description
第１図は模擬装置斜視図、第２図は電気回路図
、第３図は従来装置の一例を示す斜視図。
１０…開閉スイツチ、１１…発光体、１２…第
１の集合端子、１３…第２の集合端子、１４…コ
ネクタ、１５…第３の集合端子、１６…プリント
基板、１７…ピンリード、Ａ…シーケンス試験用
模擬装置。
FIG. 1 is a perspective view of a simulator, FIG. 2 is an electric circuit diagram, and FIG. 3 is a perspective view of an example of a conventional device. 10...Opening/closing switch, 11...Light emitter, 12...First collective terminal, 13...Second collective terminal, 14...Connector, 15...Third collective terminal, 16...Printed circuit board, 17...Pin lead, A...Sequence Simulation device for testing.
Claims (1)
ト基板の所定位置に、第１、第２、第３の集合端
子、複数個の開閉スイツチ、および発光体をそれ
ぞれ取付け、第１の集合端子とフネクタ、第２の
集合端子と開閉スイツチ、第３の集合端子と発光
体をそれぞれ接続し、上記第１、第２、第３の集
合端子を構成する各端子を抜取り可能なわたり配
線用のピンリードで接続したことを特徴とするシ
ーケンス試験用模擬装置。 ２ プリント基板の幅が、端子台の対応幅よりも
小さく設定されている上記実用新案登録請求の範
囲第１項記載のシーケンス試験用模擬装置。[Claims for Utility Model Registration] 1. Attaching first, second, and third collective terminals, a plurality of on/off switches, and a light emitting body to predetermined positions of a printed circuit board having a connector connected to a terminal block, respectively, It is possible to connect the first collective terminal to the funector, the second collective terminal to the open/close switch, and the third collective terminal to the light emitting body, and to remove each terminal constituting the first, second, and third collective terminals. A sequence test simulator characterized by connecting with pin leads for rope wiring. 2. The sequence test simulation device according to claim 1, wherein the width of the printed circuit board is set smaller than the corresponding width of the terminal block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2333585U JPS61140586U (en) | 1985-02-20 | 1985-02-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2333585U JPS61140586U (en) | 1985-02-20 | 1985-02-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61140586U true JPS61140586U (en) | 1986-08-30 |
Family
ID=30516478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2333585U Pending JPS61140586U (en) | 1985-02-20 | 1985-02-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61140586U (en) |
-
1985
- 1985-02-20 JP JP2333585U patent/JPS61140586U/ja active Pending
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