JPS6115596B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a field effect transistor, particularly a shot barrier gate type field effect transistor using a shot barrier gate for the gate.

Conventionally, so-called shot barrier gate field effect transistors (hereinafter simply referred to as SB FETs) that use a shot barrier in the gate, for example,
When a gate electrode with a length of about 1 μm is formed on a GaAs semiconductor substrate, it is possible to operate in the microwave band and is attracting attention as an ultra-high frequency band transistor. Such conventional SB FETs are shown in Figure 1a~
It was created using the manufacturing process shown in f. First, an n-type GaAs epitaxial layer 2 is grown to a predetermined thickness on a GaAs semi-insulating substrate 1 as shown in FIG. Then, a source and drain pattern is formed using photoresist 3, and an n-type pattern is formed using a known lift-off method as shown in the figure c.
A source electrode 4 and a drain electrode 5 with ohmic contact are formed on the GaAs epitaxial layer 2. Next, as shown in the figure d, a gate pattern is formed using the resist 6, and as shown in the figure e and f, the gate portion is etched by wet etching, and a recessed gate electrode 7 is formed by a lift-off method. . Figure 2 shows an enlarged view of the SB FET completed in this way. Here, as shown in FIG. 2, the thickness of the n-type GaAs epitaxial layer 2 is A, and the thickness of the trenched part is B.
and the gate length is lg.

Therefore, the biggest problem with SB FETs used in ultra-high frequency bands is to reduce the noise of the element itself, and the minimum noise figure Fo has the relationship Fo∝1/f _nax . Here, f _nax has a relationship of f _nax ∝1/lg using gate length lg. That is, to decrease the minimum noise figure Fo, the maximum oscillation frequency f _nax must be increased, and to increase the maximum oscillation frequency f _nax , the gate length lg must be decreased. However, in conventional contact exposure photolithography technology, lg=
It has been difficult to form a gate with a thickness of 1 μm or less. For this reason, methods such as electron beam exposure and ion milling have been proposed, but they require a huge amount of equipment and are suitable for gates with lg = 0.5 to 1.
A so-called submicron gate of μm is formed, but since the gate metal itself is thin, the gate resistance Rg
increases, and although the gate length lg is small,
There was a problem that the high frequency characteristics did not improve much.

This invention was made in view of the above-mentioned problems, and uses the shot barrier type gate electrode formed by the trenched list-off method as an etching mask to remove the semiconductor epitaxial layer directly under the gate electrode using the conventional wet etching method. By selectively etching using an etching method to form a submicron gate electrode, high frequency characteristics can be obtained without increasing gate resistance or requiring special equipment or complicated processes. The purpose is to provide a method for manufacturing a good SB FET.

An embodiment of the present invention will be described below with reference to the drawings.
FIG. 3 is a sectional view of a gate electrode of an SB FET according to an embodiment of the present invention. That is, the SB FET of the present invention
The manufacturing method shown in FIGS. 1a to 1f is the same as the conventional manufacturing method, and from the state shown in FIG. The epitaxial layer 2 is selectively etched by a conventional wet etching method using, for example, a phosphoric acid-based, sulfuric acid-based, or hydrochloric acid-based etching solution.

At this time, the part indicated by the dotted line in FIG. 3 is selectively etched to form the part shown by the solid line, so that the thickness of this etching is, for example, 0.3 μm.
m, the etching is stopped at a thickness B of the trenched portion of the n-type epitaxial layer 2 (B+0.3 μm), anticipating that it will be etched by 0.3 μm. After the gate electrode 7 is formed in this trenched portion, it is etched by 0.3 μm by wet etching. Then, the epitaxial layer 2 immediately below the gate electrode 7 is etched downward and side-etched from the part that is in contact with the gate electrode 7, so that the epitaxial layer 2 is etched downward as shown in FIG.
The portion 2a substantially in contact with the gate electrode 7
The length lgo of gate length lg satisfies lgo<lg. For this reason, conventional photolithography techniques were used to
=1μm gate electrode 7 is formed, lgo<l
A so-called submicron gate of μm can be easily formed.

In this way, when the n-type GaAs epitaxial layer 2 is etched by wet etching after forming the gate electrode, the trench width L ₂ becomes the conventional trench width L ₁ (see FIG. 2). ), but the third
Since almost no current flows in some regions 8 and 9 of the n-type GaAs epitaxial layer 2 on the gate electrode 7 side shown in the figure, the characteristics of the SB FET are very high at 30 GHz.
It doesn't really matter to what extent.

However, since the source-gate resistance RGs tends to increase when the frequency exceeds 30 GHz, it is necessary to prevent the width L ₂ shown in FIG. 3 from increasing.

To this end, if the width L ₁ is made as small as possible at the stage shown in FIG. 2, the spread of the width L ₂ shown in FIG. 3 can be suppressed to some extent.

As described above, the thicknesses A and B of the n-type GaAs epitaxial layer 2 shown in FIG. 3 can be made comparable to the conventional thicknesses A and B shown in FIG. gate length lgo to conventional lg
Can be made smaller. Another effect is that the gate has a so-called mesa structure, so that the gate breakdown voltage can be improved.

In the above, the thickness and impurity concentration of the semiconductor epitaxial layer can be selected as appropriate depending on the intended use of the SB FET, and the source, drain electrode, and gate electrode materials, etching liquid for the GaAs epitaxial layer, etc. can also be selected as appropriate. . Also,
Needless to say, it can be applied not only to GaAsFETs but also to other semiconductor devices.

As described above, according to the method for manufacturing a shot barrier gate field effect transistor according to the present invention, by etching the semiconductor epitaxial layer directly under the gate electrode using the gate electrode formed by the trench lift-off method as a mask, This has the effect of making it possible to manufacture SB FETs with good high frequency characteristics at extremely high yields without requiring special equipment or complicated processes.

[Brief explanation of the drawing]

Figures 1 a to f are diagrams showing the manufacturing process of a conventional SB FET, Figure 2 is an enlarged sectional view of the gate electrode portion of the recessed structure of the SB FET, and Figure 3 is an illustration of the SB FET according to an embodiment of the present invention. FIG. 3 is an enlarged cross-sectional view of a gate electrode portion. DESCRIPTION OF SYMBOLS 1... GaAs semi-insulating substrate, 2... n-type GaAs epitaxial layer, 4... source electrode, 5... drain electrode, 7... gate electrode. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A semiconductor epitaxial layer is formed on a semi-insulating semiconductor substrate, a source electrode and a gate electrode are formed on the semiconductor epitaxial layer, and a lift-off is performed by digging on the semiconductor epitaxial layer between the source electrode and the gate electrode. 1. A method for manufacturing a shot barrier gate field effect transistor, comprising forming a shot barrier gate electrode by a method, and etching the semiconductor epitaxial layer directly under the gate electrode using the gate electrode as a mask.