JPS6116594A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6116594A JPS6116594A JP13404585A JP13404585A JPS6116594A JP S6116594 A JPS6116594 A JP S6116594A JP 13404585 A JP13404585 A JP 13404585A JP 13404585 A JP13404585 A JP 13404585A JP S6116594 A JPS6116594 A JP S6116594A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- solder
- conductor wiring
- printed circuit
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は半導体装置に関する。ここでは特に半導体素子
を基板に実装した装置例えばはんだバンプ付チップ（い
わゆるＣＣＢチップ）をガラスエポキシ基板（いわゆる
プリント基板）上の導体配線（一般にはＣｕ箔）に溶融
接続した半導体装置について説明する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device. Here, we will particularly describe a device in which a semiconductor element is mounted on a substrate, such as a semiconductor device in which a chip with solder bumps (so-called CCB chip) is fused and connected to conductor wiring (generally Cu foil) on a glass epoxy substrate (so-called printed circuit board).
従来のＣＣＢ方式は半導体チップ等（以下チップと称す
る）の一方の主表面にＡ２配線を形成すると共にＡ！配
線上にパッシベーション膜を形成し、更にはんだの突起
電極を形成した後、アルミナ（Ａぷ、０．）基板上の配
線（一般にはＡｇＰｄ上にはんだディップ）電極に溶融
接続する。ＣＣＢ方式でプリント基板にチップを接続す
る場合、従来はアルミナ基板を介在物として、アルミナ
基板上にチップを溶融接続した後、アルミナ基板に設置
した導電材（普通はビン）でプリント基板に接続する実
装形態が一般的である。In the conventional CCB method, an A2 wiring is formed on one main surface of a semiconductor chip (hereinafter referred to as a chip), and an A! After forming a passivation film on the wiring and further forming a protruding solder electrode, the wiring is fused and connected to the wiring (generally solder dip on AgPd) electrode on an alumina (Ap, 0.) substrate. When connecting a chip to a printed circuit board using the CCB method, conventionally the chip is melted and connected to the alumina substrate using an alumina substrate as an intermediary, and then connected to the printed circuit board using a conductive material (usually a bottle) placed on the alumina substrate. The implementation form is common.
上記した従来技術においては、チ・ンプを一度アルミナ
基板に接続した後、プリント基板に接続するため■作業
工程が増える、■コストがアップする、等の問題が生じ
チ・ノブをプリント基板に直接接続する必要性が生じる
。しかし、もしはんだバンプ付チップを直接プリント基
板上にボンディングすれば、チップの熱膨張係数とプリ
ント基板の熱膨張係数の差により、接続部に加わる応力
が太き（なり短期間で接続部の破断に至るケースが生じ
る。In the above-mentioned conventional technology, since the tip is connected to the alumina board once and then connected to the printed circuit board, there are problems such as increasing the number of work steps and increasing cost. The need to connect arises. However, if a chip with solder bumps is bonded directly onto a printed circuit board, the difference between the coefficient of thermal expansion of the chip and the coefficient of thermal expansion of the printed circuit board will increase the stress applied to the connection (and cause the connection to break in a short period of time). There are cases where this occurs.
尚、はんだバンブ付チップ（いわゆるＣＣＢチ゛ツブ）
を用いた半導体装置については、特開昭５４−７３５６
４に記載されている。In addition, chips with solder bumps (so-called CCB chips)
Regarding semiconductor devices using
4.
本発明の目的ははんだバンブ付半導体素子を直接ガラス
エポキシ基板に実装した半導体装置を提供することであ
る。An object of the present invention is to provide a semiconductor device in which a semiconductor element with solder bumps is directly mounted on a glass epoxy substrate.
本発明の一実施例の概要は、ガラスエポキシ基板の所定
位置に貫通孔又は窪みをもち上記貫通孔上又は窪み上に
その一端が突出するように上記基板の表面に導体配線が
形成されて、上記貫通孔上・又は窪み上に突出した導体
配線に所定電極を有する半導体素子を上記所定電極と導
体配線とが固着されてなることを特徴とする半導体装置
である、次に本発明の一実施例を第１図及び第２図を基
に説明する。The outline of one embodiment of the present invention is that a glass epoxy substrate has a through hole or a depression at a predetermined position, and a conductor wiring is formed on the surface of the substrate so that one end thereof protrudes above the through hole or the depression. A semiconductor device characterized in that a semiconductor element has a predetermined electrode on a conductor wiring protruding above the through hole or recess, and the predetermined electrode and the conductor wiring are fixed to each other. An example will be explained based on FIGS. 1 and 2.
まず、第１図に示すように、所定の貫通孔２を有するプ
リント基板１の一表面に銅箔かも成る導体配線３をその
一端が上記貫通孔２上に突・出するように形成する（こ
の突出した一端を自由端７と称す）。このとき、上記導
体配線３の自由端７を同図に示すように折り曲げて形成
する。さらに上記配線３の自由端７０所定箇所に上記自
由端７全部が覆われない程度にエポキシ系樹脂からなる
絶縁物のはんだ流れ防止材４を印刷等で形成する。First, as shown in FIG. 1, a conductor wiring 3 made of copper foil is formed on one surface of a printed circuit board 1 having a predetermined through hole 2 so that one end thereof protrudes above the through hole 2 ( This protruding end is referred to as the free end 7). At this time, the free end 7 of the conductor wiring 3 is bent as shown in the figure. Further, an insulating solder flow prevention material 4 made of epoxy resin is formed at a predetermined location of the free end 70 of the wiring 3 by printing or the like to such an extent that the free end 7 is not entirely covered.
次に第２図に示すようにはんだバンブ６が付いたチップ
５を上記自由端７のはんだ流れ防止材４が形成されてい
ない箇所にはんだ接続する。Next, as shown in FIG. 2, the chip 5 with the solder bump 6 is connected by solder to the free end 7 where the solder flow prevention material 4 is not formed.
上記のような装置によればプリント基板上の導体配線に
チップを接続する前にプリント基板上の導体配線のチッ
プボンディング部をプリント基板に固定せずに自由端と
しておき、そのリードにチップを溶融ボンディングする
ため、チップボンディング後、プリント基板の熱膨張係
数とチップの熱膨張係数の差により生じる応力を上記自
由端で吸収し接続部に加わる応力が減少する。According to the above-mentioned device, before connecting the chip to the conductive wiring on the printed circuit board, the chip bonding part of the conductive wiring on the printed circuit board is left as a free end without being fixed to the printed circuit board, and the chip is melted to the lead. Because of the bonding, after chip bonding, the stress caused by the difference between the thermal expansion coefficient of the printed circuit board and the chip is absorbed by the free end, and the stress applied to the connection part is reduced.
従ってはんだバンブ付半導体素子を直接ガラスエポキシ
基板に実装することができる。又、従来のようにアルミ
ナ基板を介在する必要がないため、作業工程が減少しか
っ製造コストが下がる。Therefore, a semiconductor element with solder bumps can be directly mounted on a glass epoxy substrate. Furthermore, since there is no need to use an alumina substrate as in the conventional method, the number of work steps is reduced and the manufacturing cost is reduced.
本発明は上記した一実施例に限定されるものではなく、
例えば導体配線上に、チップに形成されるはんだパン？
°と同一融点のはんだを形成し、該はんだに上記チップ
を接続しても良い。又、逆に導体配線上に形成されるは
んだの融点がチップに形成されるはんだバンブの融点よ
りも低くし、上記チップと導体配線とを接続しても良い
。この場合、上記はんだ流れ防止材を形成しなくても良
い。The present invention is not limited to the above-mentioned example,
For example, a solder pan formed on a chip over conductor wiring?
It is also possible to form a solder having the same melting point as the solder and connect the chip to the solder. Alternatively, the chip and the conductor wiring may be connected by making the melting point of the solder formed on the conductor wiring lower than that of the solder bump formed on the chip. In this case, it is not necessary to form the solder flow prevention material.
又、上記はんだ防止材としてシリコン系樹脂及びホリイ
ミド樹脂等を使用しても良い。Furthermore, silicone resin, polyimide resin, etc. may be used as the soldering prevention material.
さらに、導体配線は、第１図のように折り曲げず貫通孔
又は年上に突出しているだけでも良い。Furthermore, the conductor wiring may not be bent as shown in FIG. 1, but may simply protrude into the through hole or above.
又、半導体チップに形成される電極は、はんだにかぎら
ず導電性の金属でも良い。Further, the electrodes formed on the semiconductor chip are not limited to solder, and may be made of conductive metal.
第１図は本発明に従って、プリント基板上に導体配線を
形成したところを示す要部断面図、第２図は本発明に従
ってプリント基板上の導体配線に半導体素子が固着され
たところを示″″ｆ′要部断面図である。
１・・・プリント基板、２・・・貫通孔、３・・・導体
配線、４・・・はんだ流れ防止材、５・・・半導体素子
、６・・・はんだバンブ、７・・・自由端。FIG. 1 is a sectional view of a main part showing conductor wiring formed on a printed circuit board according to the invention, and FIG. 2 shows a semiconductor element fixed to the conductor wiring on a printed circuit board according to the invention. f' is a sectional view of the main part. DESCRIPTION OF SYMBOLS 1... Printed circuit board, 2... Through hole, 3... Conductor wiring, 4... Solder flow prevention material, 5... Semiconductor element, 6... Solder bump, 7... Free end .
Claims (1)
板と （ｂ）上記基板上に形成された、上記貫通孔又は窪みに
その一端を突出させた導体配線と （ｃ）上記貫通孔又は窪みに突出した導体配線の一端に
固着する所定電極を持つ半導体素子とからなることを特
徴とする半導体装置。 ２、上記導体配線は、少なくともその一方の表面に絶縁
物が形成されてなる導体配線であることを特徴とする特
許請求の範囲第１項記載の半導体装置。 ３、上記半導体素子の所定の電極は、はんだ電極である
ことを特徴とする特許請求の範囲第１項記載の半導体装
置。[Claims] 1. (a) a printed circuit board having a through hole or recess at a predetermined position; (b) a conductor wiring formed on the board and having one end protruding into the through hole or recess; c) A semiconductor device comprising: a semiconductor element having a predetermined electrode fixed to one end of a conductor wiring protruding into the through hole or recess. 2. The semiconductor device according to claim 1, wherein the conductor wiring is a conductor wiring having an insulator formed on at least one surface thereof. 3. The semiconductor device according to claim 1, wherein the predetermined electrode of the semiconductor element is a solder electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13404585A JPS6116594A (en) | 1985-06-21 | 1985-06-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13404585A JPS6116594A (en) | 1985-06-21 | 1985-06-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6116594A true JPS6116594A (en) | 1986-01-24 |
Family
ID=15119074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13404585A Pending JPS6116594A (en) | 1985-06-21 | 1985-06-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6116594A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1988002210A1 (en) * | 1986-09-15 | 1988-03-24 | Baysage Pty. Ltd. | Electrical isolation device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5187967A (en) * | 1975-01-31 | 1976-07-31 | Hitachi Ltd | |
| JPS51134663A (en) * | 1975-05-16 | 1976-11-22 | Citizen Watch Co Ltd | Electronic clock circuit |
-
1985
- 1985-06-21 JP JP13404585A patent/JPS6116594A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5187967A (en) * | 1975-01-31 | 1976-07-31 | Hitachi Ltd | |
| JPS51134663A (en) * | 1975-05-16 | 1976-11-22 | Citizen Watch Co Ltd | Electronic clock circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1988002210A1 (en) * | 1986-09-15 | 1988-03-24 | Baysage Pty. Ltd. | Electrical isolation device |
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