JPS61168433U - - Google Patents
Info
- Publication number
- JPS61168433U JPS61168433U JP5224885U JP5224885U JPS61168433U JP S61168433 U JPS61168433 U JP S61168433U JP 5224885 U JP5224885 U JP 5224885U JP 5224885 U JP5224885 U JP 5224885U JP S61168433 U JPS61168433 U JP S61168433U
- Authority
- JP
- Japan
- Prior art keywords
- processing device
- data processing
- memory
- mode bit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 1
Landscapes
- Detection And Correction Of Errors (AREA)
Description
第１図はこの考案に係るデータ処理装置の一実
施例を示す回路構成図、第２図は第１図に示す装
置によるプログラムの処理手順を示す図、第３図
は従来装置を示す第１図相当図である。
図中、１はメモリ、５はパリテイチエツク回路
、１０ａ〜１０ｎ―１は非他的論理和回路である
。なお、各図中、同一符号は同一又は相当部分を
示す。
FIG. 1 is a circuit configuration diagram showing an embodiment of a data processing device according to this invention, FIG. 2 is a diagram showing a program processing procedure by the device shown in FIG. 1, and FIG. 3 is a diagram showing a conventional device. It is a figure equivalent figure. In the figure, 1 is a memory, 5 is a parity check circuit, and 10a to 10n - 1 are non-transitive OR circuits. In each figure, the same reference numerals indicate the same or equivalent parts.
Claims (1)
路を備えたデータ処理装置において、上記メモリ
からの出力データを所定の有意信号として出力可
能にするモードビツトを該メモリ内に設けて構成
したことを特徴とするデータ処理装置。 (2) 上記モードビツトを故障モードビツトとし
て構成したことを特徴とする実用新案登録請求の
範囲第(1)項記載のデータ処理装置。 (3) 上記メモリにパリテイチエツク回路を設け
るとともに、該パリテイチエツク回路によるパリ
テイエラー検出時に出力データ信号と故障モード
ビツトからの有意信号とによつて出力データ信号
を反転させる論理回路を設けて構成したことを特
徴とする実用新案登録請求の範囲第(2)項記載の
データ処理装置。[Claims for Utility Model Registration] (1) In a data processing device equipped with a circuit for detecting and correcting an output command from a memory, a mode bit that enables output data from the memory to be output as a predetermined significant signal is provided in the memory. 1. A data processing device characterized in that the data processing device is configured by being provided inside the device. (2) The data processing device according to claim 1, wherein the mode bit is configured as a failure mode bit. (3) A parity check circuit is provided in the memory, and a logic circuit is provided for inverting the output data signal based on the output data signal and the significant signal from the failure mode bit when the parity check circuit detects a parity error. A data processing device according to claim (2) of the utility model registration claim, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5224885U JPS61168433U (en) | 1985-04-09 | 1985-04-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5224885U JPS61168433U (en) | 1985-04-09 | 1985-04-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61168433U true JPS61168433U (en) | 1986-10-18 |
Family
ID=30572031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5224885U Pending JPS61168433U (en) | 1985-04-09 | 1985-04-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61168433U (en) |
-
1985
- 1985-04-09 JP JP5224885U patent/JPS61168433U/ja active Pending
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