JPS61176830U - - Google Patents

Info

Publication number
JPS61176830U
JPS61176830U JP6073785U JP6073785U JPS61176830U JP S61176830 U JPS61176830 U JP S61176830U JP 6073785 U JP6073785 U JP 6073785U JP 6073785 U JP6073785 U JP 6073785U JP S61176830 U JPS61176830 U JP S61176830U
Authority
JP
Japan
Prior art keywords
switching circuit
semiconductor switching
drains
supplied
signal lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6073785U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6073785U priority Critical patent/JPS61176830U/ja
Publication of JPS61176830U publication Critical patent/JPS61176830U/ja
Pending legal-status Critical Current

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Landscapes

  • Transforming Electric Information Into Light Information (AREA)
  • Electronic Switches (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一例の構成図、第2図〜第4
図はその説明のための図、第5図〜第7図は従来
の回路の説明のための図である。 Tは薄膜トランジスタ、Gはゲート、Sはソー
ス、Dはドレイン、Lは出力信号ライン、1o,
1eは入力信号線である。
Figure 1 is a configuration diagram of an example of the present invention, Figures 2 to 4
The figure is a diagram for explaining the same, and FIGS. 5 to 7 are diagrams for explaining the conventional circuit. T is a thin film transistor, G is a gate, S is a source, D is a drain, L is an output signal line, 1o,
1e is an input signal line.

Claims (1)

【実用新案登録請求の範囲】 平行に設けられた多数の信号線に入力信号を選
択的に供給する半導体スイツチング回路において
、 上記信号線にそれぞれ接続されるドレインが設
けられ、 上記入力信号が供給され上記ドレインの複数に
対して単一のソースが設けられ、 このソースと上記複数のドレインとの間にそれ
ぞれ制御信号が供給されるゲートが設けられてな
る半導体スイツチング回路。
[Claims for Utility Model Registration] In a semiconductor switching circuit that selectively supplies input signals to a large number of parallel signal lines, a drain is provided which is connected to each of the signal lines, and the input signal is supplied to the semiconductor switching circuit. A semiconductor switching circuit comprising a single source provided for the plurality of drains, and a gate to which a control signal is supplied between the source and the plurality of drains.
JP6073785U 1985-04-23 1985-04-23 Pending JPS61176830U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6073785U JPS61176830U (en) 1985-04-23 1985-04-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6073785U JPS61176830U (en) 1985-04-23 1985-04-23

Publications (1)

Publication Number Publication Date
JPS61176830U true JPS61176830U (en) 1986-11-05

Family

ID=30588362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6073785U Pending JPS61176830U (en) 1985-04-23 1985-04-23

Country Status (1)

Country Link
JP (1) JPS61176830U (en)

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