JPS6118425B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a time-division harmonic inverter.

This type of harmonic inverter has a main circuit configuration shown in FIG. Electrolytic capacitors CS ₁ and CS ₂ are connected in series between the positive and negative terminals of the forward converter CV.
are connected to form a DC power supply having a midpoint. The positive and negative sides of the DC power supply are connected to one ends of direct-fiber resonance commutation reactors L ₁ and L ₂ via thyristor circuits ST ₁ and ST ₂ , respectively, and the reactors L ₁ ,
The other end of _L2 is the load LR such as a work coil for induction heating.
One terminal of the load is connected to CO ₁ and the other end of the load LR
CO ₂ is connected to the midpoint of the DC power supply. The thyristor circuit ST ₁ includes a parallel circuit of a first direct circuit of thyristors S ₁₁ and S ₁₂ and a second series circuit of thyristors S ₁₃ and S ₁₄ , a common connection point of thyristors S ₁₁ and S _{12, and a connection point between thyristors S 13} and thyristors S ₁₃ , A bridge connection circuit configuration is formed in which a commutating capacitor C ₁₁ that has series resonance with a reactor L ₁ is connected between the common connection point of S ₁₄ . Similarly, the second thyristor circuit _ST2 is composed of thyristors _S21 to _S24 and commutating capacitor _C12 .

In this configuration, when the voltage polarities of the capacitors C ₁₁ and C ₁₂ are in the direction shown in the figure, the load voltage E(t) is at a change point (zero point) t ₁ from negative to positive polarity, as shown in FIG. When thyristors S ₁₁ and S ₁₄ are turned on at the same time, the equivalent circuit shown in Figure 3a is formed, and the closed loop returns from capacitor C ₁₁ to - reactor L ₁ - load LR - capacitor CS ₁ - capacitor C _{11 .} Energy is converted into sinusoidal load current I
(t) to the load LR. Then the energy stored in reactor L ₁ is transferred to capacitor C ₁₁
, the capacitor C ₁₁ is charged in the opposite direction, and at time t ₂ becomes the equivalent circuit of FIG. 3b. At time _t2 , if the voltage _Vc11 - _CS1 -E(t)>0, a reverse voltage is applied to the thyristors _S11 and _S14 to start their turn-off operation. When thyristors S ₂₁ and S ₂₄ are turned on simultaneously at time t ₂ , energy is supplied to load LR in the opposite direction to the load current. Similarly, thyristors S ₁₂ and S ₁₃ are turned on at time t ₃ and thyristors S ₂₂ and S ₂₃ are turned on at time t ₄ to complete one cycle control.

Therefore, the reverse voltage time of the thyristors, e.g. S ₁₁ and S ₁₄ , is Vc ₁₁ −CS ₁ −E(t)> under light load.
If it is 0, as shown in FIG. 4, from time t ₂ to time t ₅
However, when the load becomes heavy, the load voltage increases, and as shown by the broken line in Fig. 4, t ₂ - _{t 3}
There is a period during which Vc ₁₁ −CS ₁ −E(t)≦0 and thyristors S ₁₁ and S ₁₄ are bypassed in the forward direction, and at time t ₂ the thyristor, which has started its off operation, has commutation margin time. is less and restarts at time t′ ₂ , and t″ ₂
The reverse voltage is applied again to the thyristor, and the period t″ ₂ to _{t 5} becomes the effective reverse voltage period of the thyristor. Therefore, under heavy load, the thyristors S ₁₁ and S ₁₄ lose their gate signal at time t′ ₂ . Re-ignition occurs in a state where there is no reverse voltage, and the turn-on operation due to the reduction in reverse voltage time causes element damage.

Therefore, in the conventional harmonic inverter, as shown by the broken line in Fig. 1, diodes D ₁ and D ₂ are provided to limit the peak value _of the load voltage _. The configuration was such that a reverse voltage period of 100 kHz was ensured from time t ₁ to t ₅ . For this reason, it is not possible to obtain a high load voltage, and in order to supply the necessary power, a design must be made that allows a large current to flow.Thyristor elements and commutating capacitors are required to have large current capacities, and limiter diodes _D1 , _D2 , making it an expensive device.

The present invention was made in view of the above circumstances, and
Each thyristor S ₁₁ of thyristor circuit ST ₁ and ST ₂ ~
The firing pulses of S ₁₄ , S ₂₁ to _{S 24} are double-pulse gate currents, the first gate pulse of this gate current fires the relevant thyristor, and the second gate pulse of this gate current fires the relevant thyristor. To provide a control method for a harmonic inverter that can prevent damage to a thyristor by supplying a gate current in advance when the thyristor is about to be re-ignited due to an increase in load voltage by restriking the thyristor. With the goal.

FIG. 5 is a main circuit diagram showing an embodiment of the control device according to the present invention. Firing signal _P1 ( _S11・_S24 of thyristors S11 to _S14 , _S21 to _S24 in FIG.
S ₁₄ ), P ₂ (S ₂₁・S ₂₄ ), P ₃ (S ₁₂・S ₁₃ ), P ₄ (S ₂₂・
S ₂₃ ) generates one pulse at times t ₁ , t ₂ , t ₃ , and t ₄ for every half cycle of the load voltage according to the firing sequence shown in FIG. These ignition signals P ₁ to _{P 4} are supplied from a pulse generation circuit which uses the inverter operating frequency as a setting input, as in the conventional case. The ignition signal P ₁ and the ignition signal P ₂ are input to a NAND gate G ₁ used as an OR circuit, and the output of this NAND gate G ₁ is passed through an inverting amplifier AMP ₁ for current amplification to the input of a pulse transformer T ₁ for gate output. The output pulse of the transformer _T1 is made into a common gate pulse _P'12 of the thyristors _S11 and _S14 . Therefore, the gate pulse P ₁₂ of the thyristors S ₁₁ and S ₁₄ is the ignition signal P ₁ and P ₂
It becomes a double pulse whose phase is synchronized with each other. Similarly, NAND gates G ₂ , G ₃ , G ₄ whose gate inputs are signals P ₂ and P ₃ , P ₃ and P ₄ , P ₄ and P ₁ respectively, and amplifiers AMP ₂ , AMP ₃ , AMP which amplify the outputs thereof ₄ and gate output pulse transformers T ₂ , T ₃ , T ₄ give double pulses P ₂₃ , P ₃₄ , P ₄₁ to thyristors S ₂₁ , S ₂₄ , S ₁₃ /S ₁₂ , S ₂₂ /S ₂₃ , respectively. It will be done.

Double pulse given to thyristors S ₁₁ and S ₁₄
FIG. 6 shows voltage waveforms of thyristors S ₁₁ and S ₁₄ and their current waveforms, representing P ₁₂ . As is clear from the figure, thyristors S ₁₁ and S ₁₄ are turned on by the first pulse at time t ₁ , a half cycle of load current flows, and at time t ₂ thyristors S ₂₁ and S ₂₄ are turned on. The second pulse is given at the same timing as the first pulse. This second pulse causes the load voltage to increase across the thyristors S ₁₁ and S ₁₄
Although the current rises until the thyristor is re-ignited, the thyristor is re-ignited (t' ₂ ) with the gate current being supplied to the thyristor, thereby preventing damage to the thyristor.

Therefore, according to the present invention, irrespective of the magnitude of the load voltage, the thyristors of the thyristor circuits ST ₁ and ST ₂ are prevented from being damaged by re-ignition when no gate current is flowing, and the thyristors are prevented from being damaged even under light loads. It is possible to obtain stable high-frequency inverter operation from to heavy loads. Therefore, the output voltage E(t) can be designed to be high,
Compared to conventional devices, it is possible to supply the same amount of power with a smaller load current, and by using a thyristor circuit element with a smaller current capacity, it is possible to further reduce costs by eliminating the need for a limiter diode.

[Brief explanation of the drawing]

Fig. 1 is a main circuit configuration diagram of a time-sharing high frequency inverter, Fig. 2 is a waveform diagram for explaining the operation of each thyristor in Fig. 1, and Fig. 3 is a diagram of thyristors _S11 and _S14 in Fig. 1. FIG. 4 is an equivalent circuit diagram to explain the operation, FIG. 4 is a waveform diagram to explain the restriking of the thyristor in FIG. 1, FIG. 5 is a main part gate control circuit diagram in the present invention, and FIG. FIG. 3 is a waveform diagram for explaining the restriking of the thyristor in the invention. ST ₁ , ST ₂ ... Thyristor circuit, C ₁₁ , C ₁₂ ...
Commutation capacitor, L ₁ , L ₂ ... Commutation reactor,
LR...Load, _T1 to _T4 ...Pulse transformer.

Claims (1)

[Claims] 1 Thyristor circuits are provided on the positive and negative sides of the DC power supply, each having a commutating capacitor between the thyristor connection points of the thyristor bridge and forming a current path from the positive side thyristor through the commutating capacitor to the negative side thyristor. The output side of the thyristor circuit is commonly connected to one end of the load via a commutation reactor, and the other end of the load is connected to the midpoint of the DC power supply, and the positive terminal of the DC power supply is connected every half cycle of the load voltage. The thyristor firing control of the thyristor circuit is performed so that the load current is alternately caused to flow from the above thyristor circuit and the negative side thyristor circuit, and the charging direction of the commutating capacitor of the thyristor circuit is alternately switched, and the thyristor point of each thyristor circuit is controlled. A control method for a time-sharing harmonic inverter characterized in that the arc pulse is a double pulse that can be re-ignited in the next half cycle on the load voltage cycle.