JPS61190387A - Controller for frame buffer memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a frame buffer memory system for a scan-type display, and more particularly to a frame buffer memory system for a scanned display, which allows images to be updated rapidly while maintaining the screen data refresh rate. This invention relates to a controller for frame/notifer memory.

[Conventional technology and problems]

As the price of semiconductor memory becomes cheaper and cheaper, TESK scan type displays with frame 11/2000 pixels become more and more popular. The image to be displayed is drawn in a mass memory, which stores digital values for the brightness and/or color of each picture element, ie, pixel, on the screen. The display hardware is independent of the image content and can display any image by appropriately reading the data in the memory. In addition to providing video signal generation hardware in the frame memory to refresh the display, a memory port is also provided to allow the host computer or display processor to To change the contents of memory so that the displayed image can be changed.

Interactive graphical applications require rapid changes in displayed images, which requires rapid changes in frame notation memory. Obviously, the speed of the host processor and display processor is important for high performance, but the memory The characteristics of the system itself are also important. For some memory technologies, the substantial geometry of accessing frame-notch memory affects this rate. Conventional pixel memory systems arrange memory as words so that 16, 20, 32, or some other fixed number of pixels in a horizontal scan line on a display are accessed in a single memory cycle. In other systems, 4X4.4X5.8
A pixel array such as X8 is used as each frame, node, and word.

Conventional frame 79 memory can write pixels along horizontal lines very quickly, but is slow in most other directions. For a 17-frame buffer memory with a word width of 16 pixels and a height of 1 pixel, let the average time to perform a memory write be T seconds (including delays due to interspersed display refresh reads):
Horizontal lines can be written at a rate of 167T pixels per second. The start and end of this line are generally not on word boundaries, so the actual write rate is an average of '16/T
smaller than Next, consider vertical lines or inclined lines other than 45 degrees. All written pixels are in different words. Thus, the pixel rate is 1/T pixels per second. If we average the pixel drawing rate over all vector angles and ignore edge effects, we get about 1.36/T pixels per second. A frame node whose words correspond to pixels in a rectangular array.
In memory, the average pixel write rate is improved.

For a frame-only memory with a word of width 4 pixels and height of 4 pixels, and an average write time of T, each memory memory regardless of the direction of the line, except at the start and end of the line. - Can write 4 pixels in a cycle. Therefore, the pixel write rate is 1 second! 74/T
Reach pixel.

In turn, it is desirable to provide a means for rapidly updating images in frame memory, ie, increasing the update bandwidth.

[Means and Operations for Solving the Problems] According to the frame buffer memory controller of the present invention, images can be updated at high speed while maintaining the screen-data refresh rate.

A frame buffer memory controller controls one or more pixel depth columns (rows), which consist of one or more frame buffer memory chips per pixel. has been done. Each frame e
The memory controller receives read commands, write commands, or read modulated write commands addressed to pixels or memory chips from the display processor under its control. 7 first-in first-out commands with associated addresses and data.
-out:FIFO) and executed during the 17th memory cycle. As a result, for example, the line drawing throughput becomes n times higher. Note that n is the number of pixels per memory word.

〔Example〕

FIG. 3 generally illustrates the relationship between the present invention and a frame memory utilizing the present invention. A frame memory device has a plurality of memory elements, typically random access memories (RAMs), each of which stores one pixel in the display or frame buffer. Corresponding to one plane of bits, the word structure is as shown in FIGS. 4A-4D. In a conventional memory geometry as shown in FIG. 4A, the number of RAMs is 1.times.16.times.n. Note that n is the number of planes (the number of bits per pixel). 1024
For raster display of X1024, the capacity is 64 R
AM is required.

For each pixel or small group of pixels in the display word, a frame memory controller (FBM) is applied.
C) (241 acts as an interface with the display processor + 1/2). The controller G!41 for each frame memory is connected to the display processor
Identifies the address from the path (to), which is associated with the RAM (2', 5) under control, then the associated command/data, frame, etc., and the controller for the sofa memory ( 241 to an appropriate RAM via address and/or data paths.
and the memory location in that RAM that corresponds to the particular display word. The data to be displayed is transferred to a digital e-analog converter (DAC) C31 via the frame/nosofa/memory controller Q4 and converted into video data. The example shown in Figure 3 uses 4 bits per pixel, or 4
This is the configuration of a 16-pixel display word of the plane. A color map circuit may be provided between the frame e/q software memory controller (2) and the digital-to-analog converter C33 to determine the color of each pixel.

Figure 3 shows the frame, sofa, and memory controller (2
4+ shows pixel data for display refresh. However, an Eirin RAM with an integrated Eirin shifter, such as the TMS4161 manufactured by Texas Instruments, Incorporated, of Dallas, Texas, is equally well suited.

In either case, a color map circuit or other logic circuit may be inserted in the pixel data path before the digital-to-analog converter G2. As shown in the figure, the pixel data outputs of the frame, couch, and memory controllers (to) are connected to one set of wires (one wire per plane).
Connect to common node. In this device, each frame
The controller for the TSof memory drives the pixel data node for one pixel clock and outputs the
The power is tristated so that the next frame/transmission memory controller can send its pixel data. This is useful for low resolution displays with slow pixel-clocks. For high-resolution display, the pixel data output from the software memory controller for each frame is connected to one
It is connected to a shift φ register such as in a conventional frame memory having 51 shift registers per plane. Each shift register receives from each frame memory controller C24 as many bits or pits as there are pixels in the display word controlled by the frame memory controller C24).

The shift register in the frame controller (2) is implemented to control the pixel data output from each frame controller to the next frame controller. It is also possible to shift the final output to the color map circuit (to) or the digital-to-analog converter C33.

Details of the frame e-no-software memory controller are shown in Figure 1. The address identification circuit (to) is connected to the display control node (to) K, which determines the operation for the pixel that the memory controller controls. When a related command is received, the identified address is stored in the FIFO/S buffer (to soft part ω). During the screen Φ refresh e cycle, data is read from the RAM @ and transferred to the second F through the latch (to). The image timing circuit (41g gives the display refresh timing, and the refresh address Φ counter 14IK gives the pixel data. Address multiplier (c) sequentially addresses addresses from the refresh address counter during a refresh cycle.
! 2'3 and also during the 7 Lee memory cycle FIFO, ? RAMf the address from the sofa (to)
i to change the image. Address identification circuit (
(to) may be replaced by an external address decoder/(3?) (FIG. 3) on the display processor φnos (to). This decoder sends the command/7'-data/address to the appropriate frame software memory controller (24).

When the address identification circuit identifies the command/data word on display No. 9 as being supplied to the FLAMI 22 associated with a particular frame processor memory controller, the address information determines the command/data word on the display no. / Data information to FIFO-to each part of the sofa (to) 6G,
It accumulates in 153. In the first free memory cycle, access the appropriate RAM+2'J according to the first-in address in the address Φ(to), execute the related command in the command address ω, Write the data in the sofa 63 to RAMK one by one, or read the data one after another from this RAM and read/write the data one by one.
Either the data is stored in the processor and transferred via the display node (1) to the display processor, or the data is modified and sent to the RA via the read-modify-write (RMW) logic circuit ω.
MK rewrite.

In operation, even while reading pixel data from the memory unit and refreshing the display screen, the frame e72 buffer memory receives commands/data from the display processor via the display node. You can receive it constantly.

Command/data information is stored in FIFO along with RAM address.
・To store K and execute in the 17th memory cycle. Thus, while refreshing the display screen, the information for each pixel is stored in the frame ψ through the 7-frame memory controller.
Since it can be transferred to memory, the image on the display can be updated quickly. Furthermore, even if the vixel to be written is not a single horizontal line, all n 7-frame memories and 2 software controllers can write the pixel at the same time.
Improved performance.

Applying the same memory technique and display refresh automatic head (same average write time of 1 second) and the same word size (16 pixels), the frame number software memory shown in FIG. Pixels can be written at a rate of 16/TK.

This speed is improved by separating the frame signature memory (21m) into 16 independent partitions, one partition for each pixel in the frame/dataword. Each partition (2) has an independent address and data line controlled by the respective software memory controllers. Therefore, memory
Access is no longer limited to fixed frames, sofas,
Not limited to words.

At any given moment, each of the 16 frame memory controllers moves a pixel to a different frame A'
) You may also write in the 7a word.

In order to improve this characteristic, each frame
The memory controller Q4 controls the RAM+
It has separate address and data lines to 2'J as well as a FIFO for command-address and data from the display processor.

This FIFO sofa has two purposes.

The first purpose is to be able to continuously receive commands from the display processor even while the frame, sofa, and memory (2) are being refreshed one after another. This advantage is negligible when using video RAM. A second, more important purpose is that many display processor instructions can be sent to the memory controller ( 2
4 (same as one of the 16 sections of frame buffer memory 2) can be addressed. On average,
Display processor commands are sent to each section of memory (7 frames each) at an equal rate of 1 controller for the software memory.
24) Address ). However, in a short period of time, 1
Controller for software memory (2 frames receive most commands; FIFO) 9
The method smoothes out this uneven short period so that all partitions of memory are active most of the time.

Next, the example of FIG. 2 for a frame word having a width of 16 pixels and a height of 1 pixel will be described.

In this example, it is assumed that a line is drawn in the frame memory with a slope of 3 (the line rises by 3 pixels and 2 pixels each time it shifts to the right by 1 pixel). Also, this line is (
100, 200) to (150°50).

The first two pixel write commands address Frame Noso Sofa Memo IJ Monthly H6 (FBMC) number 5, the next three pixel write commands address FBMC number 6, and so on. If the pixel write commands are sent at a rate of 16/T per second, the controls for each frame buffer memory will be re-addressed by three additional pixel write commands. The device has just finished its last write.

In the above example, the length 3 operating at full 16/T rate
More than FIFO Nono sofa (frame with 351)
- Requires a sofa memory controller 241. For (near vertical) sloping lines, the required FIFO size is large. A reasonable FIFO sofa size can be set to one frame sofa memory controller C.
Assume 32 words per 4. Then, 32 or more slanted long lines fill the FIFO-ζ sofa of one frame-noce-sofa memory controller 124, and the display processor waits until some of the write commands are executed before continuing operation. need to wait.

In some cases, such as long vertical lines, short vertical lines do not have this problem unless several consecutive lines address the same frame/sofa memory controller C14J. 16 per second
/T Bixel works slower. In a typical 1-me,
This ratio is very small and can be brought closer to zero by increasing the FIFO size. For random short vectors, this example system with a 32-word FIFO results in approximately 13/T to 14/T pixels per second.

All performance ratings are proportional to 1/T. When using video RAM in situations where the display refresh overhead is small, T is simply the memory cycle time. If only a write is performed, T is the write cycle time. When performing a read-modify-write, T is the read-modify-write cycle time. Normal RAM 123 T-frame software memory (21mK) When used, its performance decreases depending on the proportion of time for continuous display refresh.If the refresh readout time occupies 50% of the RAM time,
T increases by a factor of 2 and performance decreases by half. However, in both cases, the relative improvement in performance by using the frame and memory controllers is the same.

Other display word configurations, such as a 4.times.4 pixel array or any other size than shown in FIGS. 4B and 4C, would work similarly. In fact, the 4x4 pixel arrangement has the slight advantage that the vertical lines address four different frame-by-frame memory controllers t241. Therefore, to satisfy FIFO Nonotsu 7 Asof,
Four times as long as the vertical line is required, and the display processor waits (by the predetermined FIFO length).

It is also possible to mix the conventional structure with the concept of a frame, sofa, and memory controller to form a single combination configuration.

For example, if you configure a 20-pixel frame Φ sofa word to be 10 pixels wide and 2 pixels high, each of the five 7-frame Φ sofa memory controllers is A 2-pixel rectangle may also be controlled.

From this K, the number of required frames, sofas, and memory controllers is reduced from 20 to 5.

In drawing vectors, each 7-frame memory month controller C can write 2 pixels at a time from a 2x2 array. Controller C for 5 frame/no-sofa memories that write independently! 41, the writing performance reaches 5 x 2/T = 10/T pixels per second. If you use all 24+ frame controllers, the rate will reach 20/T. However, if the display processor is 10/Tf xel per second, then the frame・) 9-wire Φ memory controller (the number of 24s can be reduced to 5 instead of 20 to reduce the price).

〔Effect of the invention〕

According to the invention, therefore, a controller for a frame/output memory is utilized which has a first-in first-out address for each pixel or small group of pixels within a frame address word. K
Therefore, the frame-buffer memory can improve image update bandwidth.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a preferred embodiment of the present invention, FIG. 2 is a diagram explaining the present invention in detail, FIG. 3 is a diagram showing the relationship between the present invention and frame/sofa memory, and FIG. 4A~4th
FIG. D is a diagram showing the access state of the frame, sofa, and memory. In the figure, (grabbing is 7 frames), sofa memory, is memory means, (to) is identification means, and country is first-in/first-out storage means.

Claims (1)

[Scope of Claims] Identification means for identifying information that addresses a part of a plurality of memory means constituting a frame buffer memory, and a first-in-first for temporarily storing the information from the identification means. A controller for a frame buffer memory, comprising out storage means and transfer means for transferring said information from said storage means to said memory means.