JPS6119048B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram-based data processing system.

In a data processing device having a service processor (hereinafter referred to as SVP), the SVP performs part of the processing of diagnostic commands on behalf of the user. In this case, when the central processing unit (hereinafter referred to as CPU) receives a diagnostic command, the CPU enters a halt state and requests the SVP to execute the diagnostic command. The SVP decodes this diagnostic command and performs the specified processing. This process may require access to the main memory on the CPU side. In this case, the SVP requests the CPU to execute a main memory access instruction. However, on the CPU side, there is a principle that the contents of the general-purpose registers used as the index register If you want to generate an arbitrary address that does not depend on the current contents of such general-purpose registers, conventionally you would request the SVP and CPU to execute the following instructions.

1. Save the contents of the general-purpose register you want to use to the memory in the SVP.

2 Store the address of the main memory that SVP wants to access in the above general-purpose register.

3 Request execution of command.

4 After the instruction execution is completed, restore the contents saved in the SVP to the general-purpose register.

Therefore, the conventional method described above has a problem in that it takes a long processing time to save and restore the contents of the general-purpose register to be used.

The purpose of the present invention is to save the contents of general-purpose registers and to use the contents of registers other than general-purpose registers, such as work registers, for address calculation when SVP needs to access main memory on the CPU side. The object of the present invention is to eliminate the need for restoration processing, thereby shortening processing time, and solving the problems in the conventional method described above.

Embodiments of the present invention will be described below with reference to the drawings.

The attached figure is a block circuit diagram of a data processing device having an SVP as an embodiment of the present invention. In the figure, SVP1 stores various commands for the CPU in register 2. This register 2 is also given an operation code. The control circuit 3
Generates timing signals and control signals for executing various commands from SVP1.

The control memory 4 stores various microinstructions, and the control memory 4 stores the operation code of the instruction stored in the register 2 or the operation code of the instruction stored in the instruction buffer 5 from the control circuit 3. Fixed address generated
Accessed using FA, etc. as an address. Note that 6 is an address register of the control memory 4, which is used to store the fixed address FA from the control circuit 3 or the next address specified by a microinstruction. In this manner, the control circuit 7 controls the entire apparatus shown in the figure based on the microinstructions read from the control memory 4.

In normal operation of the CPU, one instruction is selected from instruction buffer 5 and transferred to buffer 8 and registers 9 and 10 that specify general register numbers used for address calculations. General-purpose registers are selected from the general-purpose register group 11 according to the values of registers 9 and 10, and the contents of these general-purpose registers are stored in the address register 12 through ROBB and ROBX. Note that the value of the buffer 8 is also stored in the address register 12. The address calculation adder 13 performs the calculation based on the value stored in the address register 12. That is, in this case,
Address calculation is performed using the value of general-purpose register 11. The S unit 14 accesses the main memory (not shown) based on the address of the addition result of the adder 13, and then the E unit 15 performs some kind of operation. The operation results stored in the register 16 are stored in the general-purpose register 11, address calculation adder 13, S unit 14, E unit 15, and work register group 17 as necessary.
Further, the address of the control memory 4 is the instruction code selected above, and the above operation is specified by the microinstruction read from there.

Next, the case where SVP1 requests the CPU to access the main memory will be explained. In this case,
SVP1 generates an instruction execution command to register 2. Thereby, from now on, the above-described normal instruction execution processing is performed based on the operation code in register 2 instead of the operation code in instruction buffer 5.

Furthermore, work register group 1 is added to register 2.
7, the control circuit 3 sends the fixed address FA to the address register 6, and as a result, the fixed address FA is stored in the address register 6. Therefore, the control memory 4 is accessed by the fixed address FA stored in the address register 6, and as a result, the microinstruction is read out and set in the control circuit 7. As a result, data ROB1 and ROB2 of the work register group 17 are read out, and the data ROB1 and ROB2 of the work register group 17 are read out, and the data ROB1 and ROB2 of the work register group 17 are read out, and the data ROB1 and ROB2 of the work register group 17 are read out, and the data ROB1 and ROB2 of the work register group 17 are read out, and the data ROB1 and ROB2 of the work register group 17 are read out, and the data ROB1 and ROB2 of the work register group 17 are read out, and the data ROB1 and ROB2 of the work register group 17 are read out, and the data ROB1 and ROB2 of the work register group 17 are read out, and the data ROB1 and ROB2 of the work register group 17 are read out, and the data ROB1 and ROB2 of the work register group 17 are read out.
The result is stored in the calculation result register 16 via the . Next, the control circuit 7 uses the instruction code as an address to specify that the first word microinstruction to be normally executed should be read from the control memory 4. When this first word microinstruction is executed, the control circuit 3
generates a signal FF for forcibly inputting the contents of the operation result register 16 to the address calculation adder 13. As a result, the address calculation adder 13 forcibly prohibits input from the address register 12, such as data ROBB and ROBX, inputs the value of the operation result register 16, and sends the addition result to the S unit 14. do.

Note that when performing address calculation using the work register group 17 as described above, data ROB3 is set in the work register group 17 in advance by SVP1. Also, in the figure, the block labeled "SEL" indicates a selector.

As explained above, according to the present invention, SVP
When accessing main memory on the CPU side, microinstructions read from control memory using fixed addresses are used to read the values of registers other than general-purpose registers, such as work registers provided for temporarily storing data. This value is read out and stored in the operation result register of the E unit which can be the input stage of the address calculation adder, and when calculating the operand address, the value of the operation result register is forcibly input to the address calculation adder. As a result, the process of saving and restoring the contents of the general-purpose registers is no longer necessary, and therefore the processing time can be shortened, which is useful in solving the problems of the conventional method described above.

[Brief explanation of the drawing]

The accompanying drawing is a block circuit diagram of a data processing device having an SVP as an embodiment of the present invention. 1...SVP, 2...Register, 3...Control circuit, 4...Control memory, 5...Instruction buffer,
7... Control circuit, 11... General purpose register group, 12
...address register, 13...address calculation adder, 14...S unit, 15...E unit, 17...work register group.

Claims (1)

[Claims] 1. In a microprogram data processing system that sequentially retrieves microinstructions stored in a control memory and executes the instructions, a special microinstruction is executed from the control memory using a fixed address generated when a predetermined condition occurs. The content of a first register other than a general-purpose register is read by the special microinstruction, the content of the first register is stored in a second register that can be an input stage of an address adder, and when calculating an operand address, A data processing method characterized in that address calculation is performed by forcibly inputting the contents of the second register to the address adder.