JPS611930U - ECL circuit - Google Patents
ECL circuitInfo
- Publication number
- JPS611930U JPS611930U JP8690784U JP8690784U JPS611930U JP S611930 U JPS611930 U JP S611930U JP 8690784 U JP8690784 U JP 8690784U JP 8690784 U JP8690784 U JP 8690784U JP S611930 U JPS611930 U JP S611930U
- Authority
- JP
- Japan
- Prior art keywords
- ecl circuit
- electrodes
- transistors
- output
- ecl
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案に係るECL回路の一実施例を示す接続
図、第2図イ,口は従来のECL回路の接続図である。
U1・・・ECL回路、Ql,Q2・・・トランジスタ
、Rl, R2・・・負荷抵抗、R3・・・バイアス用
抵抗器。FIG. 1 is a connection diagram showing an embodiment of the ECL circuit according to the present invention, and FIG. 2A and 2B are connection diagrams of a conventional ECL circuit. U1...ECL circuit, Ql, Q2...transistor, Rl, R2...load resistor, R3...bias resistor.
Claims (1)
いる一対のベース接地形トランジスタのエミツタ電極を
それぞれ接続し、これら両トランジスタのコレクタ電極
より出力を取出すようにしたことを特徴とするECL回
路。An ECL circuit characterized in that the emitter electrodes of a pair of grounded base transistors whose base electrodes are commonly connected to both output ends of the ECL circuit are respectively connected, and the output is taken out from the collector electrodes of both transistors. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984086907U JPH062349Y2 (en) | 1984-06-12 | 1984-06-12 | ECL circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984086907U JPH062349Y2 (en) | 1984-06-12 | 1984-06-12 | ECL circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS611930U true JPS611930U (en) | 1986-01-08 |
| JPH062349Y2 JPH062349Y2 (en) | 1994-01-19 |
Family
ID=30638636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984086907U Expired - Lifetime JPH062349Y2 (en) | 1984-06-12 | 1984-06-12 | ECL circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH062349Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0228309U (en) * | 1988-08-05 | 1990-02-23 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5844822A (en) * | 1981-09-11 | 1983-03-15 | Nec Corp | Cml mutual connecting circuit |
| JPS5896425A (en) * | 1981-12-03 | 1983-06-08 | Nec Corp | Logical level converting circuit |
-
1984
- 1984-06-12 JP JP1984086907U patent/JPH062349Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5844822A (en) * | 1981-09-11 | 1983-03-15 | Nec Corp | Cml mutual connecting circuit |
| JPS5896425A (en) * | 1981-12-03 | 1983-06-08 | Nec Corp | Logical level converting circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0228309U (en) * | 1988-08-05 | 1990-02-23 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH062349Y2 (en) | 1994-01-19 |
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