JPS61206329A - Automatic equalizer - Google Patents

Abstract

PURPOSE:To obtain an automatic equalizer in which the possibility of damage to a gate constituted by a CMOS LSI is not precluded by providing a buffer amplifier amplifying a tap control signal and giving an output to a reset circuit to a tape signal generator. CONSTITUTION:When a reset signal (r) is at a state of '0', a reset circuit 122 brings the output of an AND gate G2 to a signal C13 and gives it to an integration circuit 123. When the value of a tap control signal Cn is larger than a threshold value of a non-inverting gate 124, the signal C12 is brought into a state '1' and the output of the AND gate G2 goes to the state '1', the value of the tap control signal Cn is decreased. Conversely, the tap control signal Cn is larger than the threshold value of the amplifier 124, the signal C12 and the output of the AND gate G2 goes to the state '0' and the tap control signal Cn is increased. Then the tap control signal Cn is fixed to the threshold value of the amplifier 124.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic equalizer, and more particularly to an automatic equalizer used for equalizing propagation distortion in a communication system.

[Conventional technology]

Automatic equalization devices including transversal filters are used to equalize time-varying propagation distortion in communication systems. For example, it is used to equalize propagation distortion due to selective fading in digital wireless communication systems.

Such an automatic equalizer generates a tap control signal from a data signal and an (equalized) error signal output by a demodulator used at the same time. The demodulator is inside! The carrier signal is being regenerated. If the propagation distortion due to selective fading becomes so excessive that the automatic equalizer cannot fully equalize it, the demodulator may not be able to reproduce the carrier signal. At this time, the data signal and error signal have irregular values, and therefore the tap control signal no longer corresponds to propagation distortion, so the output of the automatic equalizer becomes K with irregular distortion. Once such a state occurs, even if the selective fading is recovered, the output of the automatic equalizer will remain irregularly distorted, and the demodulator will not be able to reproduce the carrier signal and will not return to normal operation. To avoid this situation, there is an automatic equalizer that has a function to reset the demodulator to the initial state (input and output of the automatic equalizer have the same waveform) when the carrier signal cannot be reproduced. . If the automatic equalizer is reset, the demodulator can regenerate the carrier signal again and return to normal operation when selectivity 2 aging is restored.

FIG. 2 is a partial block diagram showing an example of a tap signal generator included in a conventional automatic equalizer having such a reset function. Only the portion that generates the tap control signal Cn that controls the components is shown. Therefore, the tap signal generator 13 has the same number of variable weighting circuits as the parts enclosed by the chain lines in FIG.

The portion of the tap signal generator 13 shown in FIG.
a correlation circuit 1R121 that outputs a signal C, a tap control signal Cn, and a reset signal r, and a reset circuit 122 that inputs a signal CI, and an integration circuit 123 that inputs a signal CI3 and outputs a tap control signal Cn. Configured with the necessary features. The reset circuit 122 includes an ANI gate G that receives signals C1 and reset signal r, and an AN gate G that receives an inverted signal of the reset signal and a tap control signal Cn.
It has a D gate G2 and an OR gate G which inputs the outputs of the AND gates G and G2 and outputs a signal CI3.

The integrating circuit 123 includes a resistance ratio, ・R2・R1, a capacitor C, and an operational amplifier OP that outputs a gourd tap control signal Cn.
It has A reference signal V is input to one end of the resistor R1, and the other end is connected to the positive input terminal of the operational amplifier OP.
A signal CI is input to one end of the resistor R7, and the other end is input to the resistor R8.
・One end of the parallel-connected capacitor C is commonly connected to the negative input terminal of the operational amplifier OP, and the resistor R3
- The other end of the parallel-connected capacitor C is connected to the output terminal of the operational amplifier OP.

A demodulation device used simultaneously with the automatic equalization device including the tap signal generator 13 outputs a reset signal rt- in addition to the data signal S and the error signal e. When the demodulator is normally reproducing the carrier signal, the reset signal r is in the state 11m, and when the carrier signal cannot be reproduced, the reset signal is in the state lO''.

In the tap signal generator 13, a correlation circuit 121 performs a predetermined correlation calculation to correlate the data signal S and the error signal e, and outputs the result as a signal C0. When the reset signal r is in the state IlI'', the AND gate G1 opens and the AND gate G2 closes in the reset circuit 122, so the signal CI, which is the output of the OR gate G, becomes the signal C1 itself. The output signal C13 is the signal CI itself.At this time, the integrating circuit 123 integrates and smoothes the signal C8 (i.e., the output of the correlation circuit 121) and generates the tap control signal Cn.
Output as . The tap control signal Cn controls the nth variable weighting circuit of the automatic equalizer.

When the reset signal r is in state 101, the reset circuit 12
2, the AND gate G is closed and the AND gate G2 is open, so the OR gate G is the signal CI.

The output of AND gate G2 is directly input to the integrating circuit 12 as
Output to 3. AND gate G if the value of tap control signal Cn, which is one input of AND gate G, is less than the threshold value of AND gate G;

The output becomes state #"11, and the value of the tap control signal CnO, which is the output of the integrating circuit 123, decreases. Conversely, if the value of the tap signal C'n is smaller than the threshold of the AND gate G, the AND gate The output of G is in the state "OI" and the value of the tap control signal Cn increases. Therefore, at this time, the tap control signal Cn.

The value is fixed at the threshold of AND gate G.

When the tap control signal Cn reaches this value, the nth variable weighting becomes the output of the circuit or the value 11ON. Reset signal r
When G enters the state 110'', the values of all the tap control signals are thus fixed to the threshold values of the AND gate G, so that the automatic equalizer outputs the input waveform in its entirety.

In other words, it is reset.

Now, in order to reduce power consumption, downsize, and improve productivity, the automatic equalization device uses a 0MO8 LS with as wide a range as possible.
It is desirable to configure it with I. But tap signal generator 1
If gate 3 is constructed from a MOS LSI, there is a risk that AND gate G may be damaged. As is well known, a logic circuit with a CMO8 structure includes a series-connected pair of an n-channel transistor and a p-channel transistor, and one transistor is always in an on state and the other transistor is in an off state, forming a series-connected pair. Almost no current flows. However, since the power at the input of AND gate G2 is held at the threshold value at 7 seconds, neither transistor in the series-connected pair will turn off, allowing excessive current to flow and possibly damaging them. .

As explained above, the conventional automatic equalizer has the disadvantage that the gate may be damaged if it is constructed from a CMO LSI.

[Problems to be Solved by the Invention] The problems to be solved by the present invention, in other words, the purpose of the present invention is to solve the above-mentioned drawbacks and to provide an automatic system that does not cause damage to the gate made of 0MO8 LSI. The object of the present invention is to provide an equalization device.

[Means for solving problems]

The automatic equalization device of the present invention includes a tap signal generator that includes an integrating circuit, a correlation circuit, and a reset circuit that outputs a tap control signal, and a transparsal filter that is controlled by the tap control signal, and the reset circuit that outputs the tap control signal. In the automatic equalization device, the circuit selects the output of the correlation circuit and outputs it to the integration circuit during normal operation, and selects the signal corresponding to the value of the tap control signal and outputs it to the integration circuit during reset. The signal generator includes a buffer amplifier that amplifies the tap control signal and outputs the amplified signal to the reset circuit.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments.

FIG. 1(b) is a block diagram showing an automatic equalization device 1, which is an embodiment of the present invention, and an example 2 of a demodulation device used at the same time.

The automatic equalizer I receives a received signal S and a data signal S.

・Input error signal e and reset signal r, equalize signal s2
Output. The demodulator 2 receives the equalized signal s2 and outputs a data signal S, an error signal e, and a reset signal r.

The automatic equalization device 1 includes a transparsal filter 11 and a tap signal generator 12. The transpersal filter 11 includes delay circuits T, ~T4,
It is comprised of multiplication circuits M, .about.M6 and synthesizers A, .about.A. The received signal S1 is input to the delay circuit T1, and the output of the parent circuit Tm (m is 1, 2, or 3) is input to the delay circuit Tm+1. The received signal S1 and the outputs of the delay circuits T, @T, and T4 are each divided into two parts and input into multiplication circuits M□ to M, one by one. Also, the multiplication circuit Mn
A tap control signal Cn is input to (n is an integer from 1 to 8). The outputs of the multiplication circuits M2, M4, M6, M8 and the delay circuit T are input to the synthesizer AI, and the multiplication circuits M, ・M,
The outputs of ・M and ・M7 are input to combiners A and K. The outputs of the combiners A1 and A are input to the 0 degree terminal and the 90 degree terminal of the combiner A, and the combiner A outputs an equalized signal S2.

The tap signal generator 12 generates a data signal S, an error signal e
- Inputs reset signal r and outputs tap control signal Cn.

The demodulator 2 includes a detection circuit 21 that receives the equalized signal s2 and carrier signal Cr and outputs a baseband signal s21;
It is comprised of a carrier regeneration circuit 22 that outputs a carrier signal Cr and a reset signal r, and an identification circuit 23 that receives a baseband signal S21 and outputs a data signal s3 and an error signal e.

First, the operation of demodulator 2 will be explained.

The equalized signal S is obtained by waveform equalizing the digitally modulated received signal S in the intermediate frequency band by the automatic equalizer 1, and is detected by the carrier signal Cr in the detection circuit 21 and becomes the baseband signal s21. Become. The carrier regeneration circuit 22 regenerates the carrier signal Cr, and when the carrier signal Crf is normally regenerated, the reset signal r is set to state 11".
shall be. When the carrier signal Cr cannot be reproduced, the reset signal r is changed to 9. @o l. Identification circuit 23
identifies the baseband signal S21 and the data signal S3.
Outputs error signal e. The data signal S is the received signal S
This is the signal transmitted by . The error signal e is a signal representing the deviation of the level of the baseband signal 52H from the normal level at the discrimination point, and corresponds to the equalization error of the equalized signal S.

Next, the operation of the automatic equalization device 1 will be explained.

In the transversal filter 11, the delay circuit Tk
(k is an integer from 1 to 4) outputs a signal shifted by time kT from the received signal sl. Multiplication circuit M, ・M.

operates as a variable weighting circuit and outputs the amplitude of the received signal S1 controlled by the tap control signals C1 and Ct.

Similarly, the multiplication circuits M3 to M8 receive tap control signals C8 to
C8 controls and outputs the amplitude of the output of the delay circuits TI-T and T4. The outputs of the multiplication circuits M, .M6.Ma are combined with the output of the delay circuit T by a combiner AI to equalize the common mode distortion of the received signal s.

The outputs of the multiplication circuits M8.M, .M, .M7 are synthesizer A.

The signal S is orthogonally combined with the output of the synthesizer A in the synthesizer A3 to equalize the orthogonal distortion of the received signal S.

The tap signal generator 12 has a reset signal r in a state 111.
When , the tap control signals C8 to C6 are generated from the data signal S3 and the error signal e. Also, the reset signal "is in the state"
When the value is 01, the values of the tap control signals C1 to C6 are fixed to a constant value. When the values of the tap control signals C8 to C8 reach this constant value, the outputs of the multiplication circuits M1 to M in the transversal filter 11 become 101, and the transversal filter 11 outputs only the output of the delay circuit T2. Therefore, when the reset signal is in the state "0", the automatic equalizer 1 outputs as the equalized signal S a signal that is exactly the same as the received signal S1 except for a time difference of 2T, that is, it is reset.

FIG. 1(a) is a partial diagram showing details of the tap signal generator 12 in FIG. 1 β), and only the portion that generates the tap control signal Cn is shown. The tap signal generator 12 includes eight parts that are equivalent to the parts surrounded by chain lines in FIG. 1(a).

The part shown in FIG. 1(a) inputs the tap control signal Cni to the tap signal generator 13 shown in FIG.
Buffer amplifier 1 outputs I2 to ANf) gate G,
It is configured by adding 24.

When the reset signal r is in state 1111, the tap signal generator 120 shown in FIG. 1(a) operates in the same way as the tap signal generator 13 shown in FIG. A tap control signal Cn is generated from e.

When the reset signal r is in state 1011, the reset circuit 1
22 outputs the output of the AND gate G2 to the integrating circuit 123 as a signal c13. At this time, the tap control signal CnO
If the value is greater than the threshold value of the non-inverting gate 124, the signal C12 will be in the state 1'111, and the output of the AND gate G2 will also be in the state 11", so the value of the tap control signal Cn will decrease. Conversely, the value of the tap control signal Cn will decrease. The value of the control signal Cn is determined by the amplifier 124.
is smaller than the threshold value of , the output of signal CI2 and AND gate G becomes state 10@, and the value of tap control signal Cn increases. Therefore, it was evening at this time.

The value of the amplifier control signal Cn is fixed to the threshold value of the amplifier 124. When the tap control signals C1 to C8 of this value are input, the outputs of the multiplication circuits M, to M6 of the transversal filter 11 become the value 1lOI, and the automatic equalizer 1 is reset.

At the time of reset, the n signal CI2 repeats the states 111 and 1lol, and does not remain near the threshold value of the AND gate G.

There is no risk of damage. As the amplifier 124, an amplifier is used that is not likely to be damaged even if its input value is maintained at a threshold value. For example, TTL (transist
or transistor logic), an amplifier may be used.

〔Effect of the invention〕

As explained in detail above, since the present invention uses a means of providing an amplifier that gates the tap control signal, the automatic equalization device of the present invention can be configured with a CMO8 LSI without fear of damage. This has the effect of reducing power consumption, downsizing, and improving productivity.

[Brief explanation of drawings]

FIG. 1(a) is a partial block diagram showing details of the tap signal generator 12 in FIG. 1(bl), FIG. 1(b) is an embodiment of the automatic equalization device of the present invention,
FIG. 2 is a partial block diagram showing an example of a tap signal generator included in a conventional automatic equalization device. 121...Correlation circuit, 122...Reset circuit, 123...Integrator circuit, 124...
...buffer amplifier. ii, ;:X, ノ'. C/I"-C10: No. a V: 9'! No. I'A
Cw:%tbutsmtv$l Figure C0-) $21! r

Claims (1)

[Scope of Claims] A tap signal generator comprising an integrating circuit, a correlation circuit, and a reset circuit that outputs a tap control signal, and a transversal filter controlled by the tap control signal,
In an automatic equalization device, the reset circuit selects the output of the correlation circuit and outputs it to the integration circuit during normal operation, and selects a signal corresponding to the value of the tap control signal and outputs it to the integration circuit during reset, The automatic equalization device is characterized in that the tap signal generator includes a buffer amplifier that amplifies the tap control signal and outputs the amplified signal to the reset circuit.