JPS6120830A - Optical integration circuit - Google Patents

Optical integration circuit

Info

Publication number
JPS6120830A
JPS6120830A JP14179384A JP14179384A JPS6120830A JP S6120830 A JPS6120830 A JP S6120830A JP 14179384 A JP14179384 A JP 14179384A JP 14179384 A JP14179384 A JP 14179384A JP S6120830 A JPS6120830 A JP S6120830A
Authority
JP
Japan
Prior art keywords
capacitor
voltage
circuit
light incident
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14179384A
Other languages
Japanese (ja)
Inventor
Koichi Omori
大森 功一
Toshiyuki Kumakura
敏之 熊倉
Hiroyuki Kataoka
片岡 博之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP14179384A priority Critical patent/JPS6120830A/en
Priority to DE19853524375 priority patent/DE3524375A1/en
Publication of JPS6120830A publication Critical patent/JPS6120830A/en
Priority to US07/107,879 priority patent/US4808811A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01JMEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00Photometry, e.g. photographic exposure meter
    • G01J1/42Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44Electric circuits
    • G01J1/46Electric circuits using a capacitor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Photometry And Measurement Of Optical Pulse Characteristics (AREA)

Abstract

PURPOSE:To detect accurately the quantity of photodetection and to reduce the size of the circuit by providing plural transistors (Tr) for expansion. CONSTITUTION:Plural Trs 11' and 11'' which have a common base, emitter, and collector with a Tr11 are provided. Therefore, the signal of a photocurrent generated by a photodiode PD1 and converted into a voltage through Trs 11, 11', and 11'' connected to an operational amplifier 10 through a diode 12 is charged in a capacitor 12' as a current expanded through the plural Trs 11, 11', and 11''. Therefore, a logarithmic relation is born between the terminal voltage of the capacitor 12' and the quantity of light incident on the PD1, and even when the quantity of light incident on the PD1 is extremely small, the optical integration circuit is combine with a dimming circuit which raises the voltage of a reference voltage source by a specific value every time a dimming level is doubled, thereby reducing an error.

Description

【発明の詳細な説明】 本発明は光の量を電気信号に変換する光積分回路に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an optical integration circuit that converts the amount of light into an electrical signal.

従来の基本的な光積分回路はダイナミックレンジが光の
量の変化に対して充分ではなかった。
The dynamic range of conventional basic optical integration circuits was not sufficient for changes in the amount of light.

以下第1図を用いて説明する。第1図に示した従来の光
積分回路はホトダイオード1に入射する光によりホトダ
イオード1に生じる光電流をコンデンサ2に蓄え、コン
デンサ2の端子電圧を基準電圧源5の電圧とコンパレー
タ4で比較することによシホトダイオードに入射する光
の量を検出するように構成されていた。
This will be explained below using FIG. The conventional optical integration circuit shown in FIG. 1 stores the photocurrent generated in the photodiode 1 due to light incident on the photodiode 1 in a capacitor 2, and compares the terminal voltage of the capacitor 2 with the voltage of a reference voltage source 5 using a comparator 4. It was configured to detect the amount of light incident on the photodiode.

基準電圧源5の発生する電圧を最小18mVから2v程
度とすると第1図に示した光積分回路のダイナミックレ
ンジすなわち最小電圧と最大電圧の比は2 V/1 S
 mv中27  となり、アペックス値で表現すると7
段程度しか得られないことになる。
If the voltage generated by the reference voltage source 5 is set from a minimum of 18 mV to about 2 V, the dynamic range of the optical integrator circuit shown in FIG. 1, that is, the ratio of the minimum voltage to the maximum voltage, is 2 V/1 S.
It becomes 27 in mv, which is 7 when expressed in apex value.
You will only be able to get a grade.

ところでストロボ装置をTTL調光で用いようとすると
該ストロボ装置の調光装置の光積分回路においてはフィ
ルム感度の種類が1806から工806400まで、撮
影レンズの絞シはFlからからF32までそれぞれアペ
ックス値に換算すると10段のダイナミックレンジが必
要であるためフィルム感度、絞シの両者がそれぞれ独立
に変化する場合ではアペックス値に換算して20段のダ
イナミックレンジが必要となる。
By the way, when trying to use a strobe device with TTL flash control, the light integrating circuit of the flash control device of the strobe device has film sensitivity types ranging from 1806 to 806,400, and apex values of the photographic lens aperture ranging from Fl to F32. When converted into an apex value, a dynamic range of 10 steps is required. Therefore, when both the film sensitivity and aperture change independently, a dynamic range of 20 steps is required when converted to an apex value.

したがって前述の光積分回路をストロボ装置に用いて光
量の制御を行おうとするとダイナミックレンジが不足と
なって晃量制御を行うことができなかった。このためホ
トダイオードによシ出力される光電流を対数圧縮するこ
とによシ光積分回路としてのダイナミックレンジを大き
くした回路が第2図に示すように知られている。
Therefore, if an attempt was made to control the amount of light by using the above-mentioned optical integration circuit in a strobe device, the dynamic range would be insufficient, making it impossible to control the amount of light. For this reason, a circuit is known, as shown in FIG. 2, in which the dynamic range of the optical integration circuit is increased by logarithmically compressing the photocurrent outputted by the photodiode.

第2図に示す光積分回路においては圧縮用ダイオード1
2をオペアンプ10の負帰遷路に挿入してオペアンプ1
0の出力を伸長するトランジスタ11のエミッタにコン
デンサ2を接続している。
In the optical integration circuit shown in Fig. 2, the compression diode 1
2 into the negative feedback transition path of operational amplifier 10 and
A capacitor 2 is connected to the emitter of a transistor 11 that extends the output of 0.

ここでホトダイオード1を流れる光電流をHpとすると
トランジスタ11のベースの電圧■bけ以下の式で表わ
される。
Here, if the photocurrent flowing through the photodiode 1 is Hp, it is expressed by the following equation below the voltage of the base of the transistor 11.

T  1p Vb=−ぎn −(1) 1s 18:ダイオードの逆飽和電流 に:ポルツマ/係数 T:絶対温度 q:電子の電荷 またトランジスター1のエミッタ電流を1(t)とし、
コンデンサ2の端子電圧をVcとすると以下の式で表わ
される。
T 1p Vb=-gin-(1) 1s 18: For the reverse saturation current of the diode: Portsma/coefficient T: Absolute temperature q: Charge of electrons Also, let the emitter current of transistor 1 be 1(t),
Letting the terminal voltage of the capacitor 2 be Vc, it is expressed by the following equation.

ここで1 (1)はトランジスタ110ベースエミツタ
間の電圧で決まシ、以下式で表わされる。
Here, 1 (1) is determined by the voltage between the base and emitter of the transistor 110, and is expressed by the following equation.

1(t) == is 8Xp (−(Vb−Vc) 
)   (3)T 結論だけを記すとコンデンサ2の端子電圧Vcけつぎの
式で表わされる。
1(t) == is 8Xp (-(Vb-Vc)
) (3) T To state only the conclusion, the terminal voltage Vc of capacitor 2 is expressed by the following equation.

Vc = αln (1;L+1 )        
      (4)同αQはαニー Q=Of Ipdt  (Oは定数)により決まる。
Vc = αln (1; L+1)
(4) αQ is determined by αkneeQ=Of Ipdt (O is a constant).

ここでαは知られているそれぞれの定数から常温では約
26 mVである。ここでQが1に対して非常に大きい
場合はQが2倍になることによりVQ(7)値は18m
V (= 0.026 /n2)だけ増加することにな
る。すなわちホトダイオード1に入射する光量が2倍に
なるとコンデンサ2の端子電圧Vcは18mV増加する
Here, α is approximately 26 mV at room temperature based on known constants. Here, if Q is very large compared to 1, the VQ(7) value will be 18m by doubling Q.
It will increase by V (= 0.026/n2). That is, when the amount of light incident on the photodiode 1 doubles, the terminal voltage Vc of the capacitor 2 increases by 18 mV.

ここで基準電圧発生器5の出力電圧を18 mVから1
800 mVまで変化させればアペックス値を100段
のダイナミックレンジを得るととができる。
Here, the output voltage of the reference voltage generator 5 is changed from 18 mV to 1
If the apex value is changed to 800 mV, a dynamic range of 100 steps can be obtained.

しかしながら第2図に示した光積分回路のコンデンサの
端子電圧を示す(4)式は、真数の項にGL+1を含ん
でいるため第4図の1に示すようにQが1に対して充分
大きい場合にはホトダイオード1に入射した光量とコン
デンサ2の端子電圧との間には対数関係が成り立つが、
Qが1に対して充分大きくない場合にはホトダイオード
1に入射した光量とコンデンサ2の端子電圧との間には
対数関係が成シ立たなくなる。同第4図(a)は(4)
式のグラフであシ、第4図(1,)はその数値を表にし
た図である。例えば第4図の1に示すようにQが充分大
きい領域ではQが2倍になるとコンデンサの端子電圧は
18mV増加するが、Qが1に対して近い数において2
倍になる場合、例えばQが2から4に変化する際にはコ
ンデンサの端子電圧は13.2mVl、か増加しない。
However, since equation (4) showing the terminal voltage of the capacitor of the optical integrating circuit shown in Figure 2 includes GL+1 in the antilog term, Q is sufficient for 1 as shown in 1 in Figure 4. If it is large, a logarithmic relationship holds between the amount of light incident on the photodiode 1 and the terminal voltage of the capacitor 2, but
If Q is not sufficiently large relative to 1, a logarithmic relationship will not hold between the amount of light incident on the photodiode 1 and the terminal voltage of the capacitor 2. Figure 4(a) is (4)
The graph of the equation is shown in FIG. 4 (1,), which is a table showing the numerical values. For example, as shown in 1 in Figure 4, in a region where Q is sufficiently large, when Q doubles, the terminal voltage of the capacitor increases by 18 mV, but when Q is close to 1,
In the case of doubling, for example, when Q changes from 2 to 4, the terminal voltage of the capacitor does not increase by 13.2 mVl.

ところで一般にストロボ装置の調光レベルはアペックス
値に換算してアペックス値が1段増加すると調光レベル
を示す基準レベルは一定値に増加させるように構成され
ている。したがって前述の光積分回路をストロボ装置の
調光回路に用いる際の調光レベルが低いとき、すなわち
ス光を停止させるような場合には前述のようにホトダイ
オードの受光光量とコンデンサの端子電圧との間に対数
関係が成シ立たないため調光レベルに大きな誤差が生じ
てストロボ撮影の際、適正露光を得ることができなかっ
た。ところで被写体に向けて比較的弱い光でブリ発光し
、該プリ発光の反射光レベルルに応じて主発光を制御す
るストロボ装置の場合にはプリ発光量が小さいだけに該
ブリ発光の反射光レベルは極めて低いため、前述のよう
な光積分回路を用いるとすると反射光レベルを正確に測
定することができなくなシ、主発光を正確に制御するこ
とができないという欠点が更に大きく問題となる。
Generally, the light control level of a flash device is converted into an apex value, and when the apex value increases by one step, the reference level indicating the light control level is increased to a constant value. Therefore, when the above-mentioned optical integration circuit is used in the dimming circuit of a strobe device, when the dimming level is low, that is, when the flash is stopped, the amount of light received by the photodiode and the terminal voltage of the capacitor are Since there is no logarithmic relationship between the two, a large error occurs in the light control level, making it impossible to obtain proper exposure during strobe photography. By the way, in the case of a strobe device that emits relatively weak light towards the subject and controls the main flash according to the reflected light level of the pre-flash, the reflected light level of the blur-flash is small because the amount of pre-flash is small. Since this is extremely low, if an optical integration circuit such as the one described above is used, the reflected light level cannot be accurately measured, and the main light emission cannot be accurately controlled, which becomes an even bigger problem.

本発明は上述の従来の光積分回路の欠点を解消してホト
ダイオードの受光光量が極めて低いレベルにおいても正
確に受光光量の検出ができるような光積分回路を提供す
ることを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide an optical integrator circuit which eliminates the drawbacks of the conventional optical integrator circuit described above and can accurately detect the amount of light received by a photodiode even when the amount of light received by a photodiode is extremely low.

以下図面を用いて本発明を詳述する。The present invention will be explained in detail below using the drawings.

第3図は本発明の一実施例のブロック図である。第3図
において、第1図、第2図に示した素子と同じ機能をも
つ素子には同じ符号を付し説明を省略する。
FIG. 3 is a block diagram of one embodiment of the present invention. In FIG. 3, elements having the same functions as the elements shown in FIGS. 1 and 2 are given the same reference numerals, and their explanations will be omitted.

かかる図において11’、11’はトランジスタ11と
ベース、エミッタ、コレクタを共通にするトランジスタ
であル、少なくとも2つ以上設けられる。伺トランジス
タ11とベース、エミッタ、コレクタを共通にするトラ
ンジスタを複数個設ける代わシに、オペアンプ10の帰
遍路に設けられたダイオード接続されているトランジス
タのベースエミッタ間の接合面積の複数倍の面積のペー
スエミッタ間の接合面積を有するトランジスタを設けて
も同じ効果が期待で自る。
In this figure, reference numerals 11' and 11' indicate transistors having a common base, emitter, and collector with the transistor 11, and at least two transistors are provided. Instead of providing a plurality of transistors that share a base, emitter, and collector with the operational amplifier 11, a transistor with an area multiple times the junction area between the base and emitter of the diode-connected transistor provided in the return path of the operational amplifier 10 is used. The same effect can be expected by providing a transistor having a junction area between pace emitters.

以上の様に構成された本発明の実施例の動作について説
明する。
The operation of the embodiment of the present invention configured as above will be explained.

本実施例においてはトランジスタ11とベース、エミッ
タ、コレクタを共通にするトランジスタを複数設けてい
る。
In this embodiment, a plurality of transistors having a common base, emitter, and collector with the transistor 11 are provided.

したがってオペアンプ10とダイオード接続されたトラ
ンジスタによって電流−電圧変換されて圧縮されたホト
ダイオード1で発生する光電流の信号は前記複数のトラ
ンジスタそれぞれKより伸長された電流となってコンデ
ンサ2を充電させる。したがってコンデンサ2の端子電
圧V (t)は以下の式で表わされる。
Therefore, the photocurrent signal generated in the photodiode 1 which is current-to-voltage converted and compressed by the operational amplifier 10 and the diode-connected transistor becomes a current extended by each of the plurality of transistors K, and charges the capacitor 2. Therefore, the terminal voltage V (t) of the capacitor 2 is expressed by the following equation.

V (t) = Q /n(nQ、+1 )ここでnは
トランジスタ11とベースエミッタ、コレクタを共通に
接続されたトランジスタの個数である。
V (t) = Q /n (nQ, +1) where n is the number of transistors whose base emitters and collectors are commonly connected to the transistor 11.

したがって上述の式においてQ>1となるようなnを設
定すれば、すなわちトランジスタ11とベース、エミッ
タ、コレクタを共通にするトランジスタを適当な敷設け
ればコンデンサ2の端子電圧v (t)は以下の式で近
似される。
Therefore, if n is set such that Q > 1 in the above equation, that is, if an appropriate transistor is installed that shares the base, emitter, and collector with transistor 11, the terminal voltage v (t) of capacitor 2 will be as follows. It is approximated by Eq.

V(t)4=α1nnQ。V(t)4=α1nnQ.

すなわちコンデンサ2の端子電圧V(t)とホトダイオ
ード1に入射する光量とは第4図(a) (b)の(I
I)に示すように対数関係が成シ立つ。
That is, the terminal voltage V(t) of the capacitor 2 and the amount of light incident on the photodiode 1 are expressed as (I) in FIGS. 4(a) and (b).
A logarithmic relationship holds as shown in I).

したがってホトダイオード1に入射する光量が非常に小
さい場合でも入射光量が2倍になる毎にコンデンサ2の
端子電圧は18mVづつ増加することになる。
Therefore, even if the amount of light incident on the photodiode 1 is very small, the terminal voltage of the capacitor 2 will increase by 18 mV every time the amount of incident light is doubled.

すなわち調光レベルをアペックス値にて制御する言い換
えれば調光レベルを2倍にする毎に基準電圧源の電圧を
一定値毎増加させる調光回路に本実施例の光積分回路を
組み合わせれば、誤差を極めて小さくできる。
That is, if the optical integration circuit of this embodiment is combined with a dimming circuit that controls the dimming level using the apex value, in other words, increases the voltage of the reference voltage source by a fixed value every time the dimming level is doubled. Errors can be made extremely small.

以上説明した様に本発明に依れば受光素子に入射する光
により生じる光電流を対数圧縮して、該対数圧縮された
信号を伸長用トランジスタで伸長して生じる電流によシ
前記伸長用トランジスタのエミッタに゛接続されたコン
デンサを充電することによシ前記受光素子に入射した光
量を積分する光積分回路において前記伸長用トランジス
タを複数並列に接続したので従来の光積分回路の様に前
記受光素子に入射する光量が小さい領域においては受光
素子に入射する光量と前記コンデンサの端子電圧との間
に対数関係が成シ立だなかったという欠点を解消して受
光素子に入射する光量が小さい領域であっても受光素子
に入射する光量と前記コンデンサの端子電圧との間にほ
ぼ対数関係が成り立つ光積分回路を実現できた。
As explained above, according to the present invention, the photocurrent generated by the light incident on the light receiving element is logarithmically compressed, and the logarithmically compressed signal is expanded by the expansion transistor. Since a plurality of the extension transistors are connected in parallel in the optical integration circuit that integrates the amount of light incident on the light receiving element by charging the capacitor connected to the emitter of the In a region where the amount of light incident on the element is small, the disadvantage that a logarithmic relationship does not hold between the amount of light incident on the light receiving element and the terminal voltage of the capacitor is solved, and the amount of light incident on the light receiving element is small. It was possible to realize an optical integrator circuit in which a nearly logarithmic relationship is established between the amount of light incident on the light receiving element and the terminal voltage of the capacitor even in the area.

更に本発明に依れば従来の光積分回路が伸長ンサの充電
電流が大きくなり、受光素子としては比較的lト型の安
価なホトダイオードを用いることができるばかりか光積
分回路を小型化する効果を奏する。
Furthermore, according to the present invention, the charging current of the extension sensor becomes larger in the conventional optical integrating circuit, and a relatively inexpensive photodiode of L type can be used as the light receiving element, and the optical integrating circuit can be miniaturized. play.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の光積分回路の回路図、 第2図は第1図の光積分回路を改良した従来の光積分回
路の回路図、 第3図は本発明の一実施例の回路図・ 第4図(a) l (b)は第2図、第3図に示したコ
ンデンサの端子電圧と受光光量との関係を示す図である
。 1 ・・・ホトダイオード ’11,11’、11’・・・伸長用トランジスタ12
・・・圧縮用ダイオード
Fig. 1 is a circuit diagram of a conventional optical integrator circuit, Fig. 2 is a circuit diagram of a conventional optical integrator circuit that is an improved version of the optical integrator circuit in Fig. 1, and Fig. 3 is a circuit diagram of an embodiment of the present invention. FIGS. 4(a) and 4(b) are diagrams showing the relationship between the terminal voltage of the capacitor shown in FIGS. 2 and 3 and the amount of received light. 1... Photodiode '11, 11', 11'... Extension transistor 12
・・・Compression diode

Claims (1)

【特許請求の範囲】[Claims] 受光素子に入射する光により生じる光電流を対数圧縮し
て、該対数圧縮された信号を伸長用トランジスタで伸長
して生じる電流により前記伸長用トランジスタのエミッ
タに接続されたコンデンサを充電することにより前記受
光素子に入射した光量を積分する光積分回路において、
前記伸長用トランジスタを複数並列に接続することを特
徴とする光積分回路。
The photocurrent generated by the light incident on the light receiving element is logarithmically compressed, and the logarithmically compressed signal is expanded by an expansion transistor, and the generated current charges a capacitor connected to the emitter of the expansion transistor. In the optical integration circuit that integrates the amount of light incident on the light receiving element,
An optical integration circuit characterized in that a plurality of the extension transistors are connected in parallel.
JP14179384A 1984-07-09 1984-07-09 Optical integration circuit Pending JPS6120830A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP14179384A JPS6120830A (en) 1984-07-09 1984-07-09 Optical integration circuit
DE19853524375 DE3524375A1 (en) 1984-07-09 1985-07-08 LIGHT MEASURING
US07/107,879 US4808811A (en) 1984-07-09 1987-10-09 Light integrating circuit for use in a light measuring device which is accurate for both low and high light values

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14179384A JPS6120830A (en) 1984-07-09 1984-07-09 Optical integration circuit

Publications (1)

Publication Number Publication Date
JPS6120830A true JPS6120830A (en) 1986-01-29

Family

ID=15300273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14179384A Pending JPS6120830A (en) 1984-07-09 1984-07-09 Optical integration circuit

Country Status (1)

Country Link
JP (1) JPS6120830A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007240260A (en) * 2006-03-07 2007-09-20 Stanley Electric Co Ltd Light intensity detection circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007240260A (en) * 2006-03-07 2007-09-20 Stanley Electric Co Ltd Light intensity detection circuit

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