JPS6120880B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention captures a time series of physical quantities extracted from an input voice signal, that is, a speaker's voice wave, as a characteristic pattern, and compares this with a pre-registered pattern to recognize a voice signal command. The present invention relates to a speech recognition device using a pattern matching method, and more particularly to a speech recognition device in which means for determining similarity between patterns is provided with means for preventing erroneous recognition of speech. In general, there are two methods for speech recognition: a method that directly calculates the similarity between a feature (input) pattern obtained after extracting some features from an audio signal and a registered pattern that has been registered in advance; Later, this was replaced with a phonological sequence,
There are two main methods: a method that calculates the degree of similarity by comparing this with a word dictionary (pattern) registered in advance. Of these two methods,
The latter is advantageous for speech recognition when there are many words because it identifies phonological units. However, when the number of words is not so large, the former pattern matching recognition generally provides a higher recognition rate. An example of a speech recognition system using pattern matching, in which the number of words to be recognized is about several dozen, is used in consumer equipment, for example, when a television receiver is controlled by voice.
In other words, to control the television receiver's power control, volume control, channel switching, etc., the voice of the words expressing the control content is registered in advance in the voice recognition device, and the voice is stored in the response device as a recognition response. This is a case in which the voice command and the registered control content are checked, and if they match, a voice response is sent to indicate that the control content has been recognized, and a predetermined control is performed. For example, when selecting one channel in channel switching control, "1
When you memorize the voice ``Channel'' as a registered pattern, when you face the microphone that receives the voice command and give the voice command ``1 channel'', the voice response will say ``OK'' and the 1st channel will be activated. The channel is selected. However, the problem here is that when the voice command "1 channel" is given, a voice command "8 channels", which has a similar sound, is registered as a control pattern (registered pattern). . That is, the sounds of both "ichi" and "hachi" are similar, and the problem is how to prevent the mistaken speech recognition of "ichi" and "hachi". This is because in the words "ichi" and "hachi", the vocal energy of the pronunciation part of "chi" is large, making it difficult to distinguish between "i" and "ha". Generally, when there is an accented voice in one word, the voice energy is concentrated in that part, making it difficult to recognize the voice information in other parts. Therefore, when performing voice recognition, it is necessary to compare the characteristic (input) pattern and the registered pattern without losing information on parts of the voice command other than the strong sounds. Furthermore, when a speaker generates a voice, the amplitude changes each time the speaker utters the same word. Therefore, in speech recognition, it is necessary to always obtain the same pattern for the same word even if the amplitude changes. Further, the voice used when registering the control content as a registered pattern by voice does not necessarily match the rate of voice emitted as a voice command. This means that after a certain word is registered, even if the word is uttered in the same way again, the word length will be different. Therefore, when evaluating the similarity between the input pattern and the registered pattern, erroneous recognition will occur unless the time axis is also taken into account. Furthermore, when a speaker utters a word, even during the utterance period of one word, there is a period in which the utterance becomes a voiceless sound. This unvoiced sound part data not only does not contribute much to speech recognition, but it often worsens the recognition rate. In particular, in the case of numbers such as ``ichi'' and ``hachi'', both include a silent part in the center, and even in the part where the voice is uttered, the only difference between the two is the ``i'' and ``ha'' parts. be. In such a case, if the length of the silent part changes during utterance, there is a possibility that "ichi" may be mistakenly recognized as "hachi", or conversely, "hachi" may be mistakenly recognized as "ichi". It is an object of the present invention to provide a speech recognition device that can solve the above-mentioned problems, particularly the problem of erroneous recognition of speech caused by the presence of silent parts. Embodiments of the present invention will be described in detail below with reference to the drawings. First, in order to make the present invention easier to understand, a speech recognition device based on a pattern matching method currently being considered is shown in FIGS. 8, and then an embodiment of the present invention will be described using FIG. 1 and FIGS. 9 to 16. In speech recognition using the so-called pattern matching method, speech recognition is performed by determining the degree of similarity between an input pattern indicating the characteristics of the input speech and a registered pattern in which predetermined words are registered. The misrecognition rate is affected by the method of feature extraction due to the points mentioned above. Therefore, in the present invention, when extracting the features of the input pattern, the amplitude and time axis of the input audio are normalized to prevent misrecognition, and furthermore, the similarity between the two patterns is calculated. Simplified speech recognition devices have been devised. FIG. 1 is a circuit block diagram showing such a speech recognition device, which converts sound pressure vibrations caused by vocalization into electrical signals using a microphone, and further flattens the frequency distribution of the speech. An input section 1, a feature extraction section 2 that extracts the features from the audio signal converted into an electrical signal obtained by the audio input section 1, and a feature extraction section 2 that stores the features extracted by the feature extraction section 2 and combines them with the input pattern. It has a recognition processing section 3 that performs arithmetic processing of comparison between the following and discriminates a control command by voice, and a voice response section 4 that responds by voice that the control command has been recognized is added as necessary. This voice response unit 4 includes a memory unit 401 that stores words to be responded to as patterns, and a second I/O (input/output) port 40.
2. It has a control unit 403, a D/A converter 404, and a low-pass filter 405, and responds by voice from the voice circuit of a controlled device such as a television receiver 406 to indicate that the speaker's voice command has been recognized. do. In the audio input section 1, input audio is converted into FM waves by a wireless microphone 11, received by an FM receiver 12, and inputted to a preamplifier 13, and inputted by a microphone 14 provided before the preamplifier 13. It can be incorporated into the system in any of the following ways. In any of these forms, the SN ratio, which is the ratio between the audio signal necessary for recognition and other audio signals, mainly depends on the directivity of the microphone, so the microphones 11 and 14 are unidirectional. Use sexual items. The audio signal obtained by the preamplifier 13 and converted into an electric signal has its high frequency range emphasized by the pre-emphasis circuit 15 in order to improve the intelligibility of monosyllables. The output of the voice input section 1 obtained in this manner is supplied to the feature extraction section 2, where the feature data necessary for input and formation of the registered pattern is extracted. In other words, the frequency is captured in time series from the speaker's voice wave, the voice is frequency-analyzed, this data is sampled at regular time intervals, and the sampled analog data is converted to A/D.
Convert to digital quantity using a converter. That is, switched capacitor bandpass filters (hereinafter referred to as BPF) indicated by 16 ₁ to 16 ₁₅ are connected to the input terminal of the feature extraction unit 2. This one
The center frequency of the BPFs ₆₁ to ₁₆₁₅ is determined by the applied clock, and each filter characteristic is a 6th _- order Thiepisief characteristic and has an attenuation characteristic of approximately -36aB/OCT.
Approximately 200Hz to 6.4KHz band at 1/3 octave intervals
Separated into 15 bands. The audio signals of the band components of these 15 bands are passed through 16 _{1 to 1}
Each of the BPFs ₅ includes a sample and hold circuit 17 that samples and holds the signal at approximately 20m _sec intervals.
_{1 to 15} are connected, and feature data of the incoming voice is extracted by this sample and hold action. In this way, the sample and hold circuit 17 ₁
The feature data extracted in _{15 to 15} is an analog quantity, but for example, an 8-bit A/D converter (analog -
It is converted into a digital quantity by a digital converter) 18. At this time, switching control between the sample and hold circuits 17 _{1 - 15} and the A/D converter 18 is performed by a multiplexer 19 . Therefore, the A/D converter 18 obtains a digitized amount of the time-frequency-level characteristics shown in FIG. 2 extracted from the audio signal. The voice feature data extracted by this A/D converter 18 is supplied to the recognition processing section 3 via a first I/O (input/output) port 20. The recognition processing unit 3 includes a registration pattern memory for storing and registering the voice characteristics extracted from the command voice when instructing control contents, such as specifying a channel to receive or controlling power on/off, by voice. 21. Input pattern memory 22 for storing the characteristics of the instruction voice as an input pattern when the speaker utters the desired control content;
A system program memory 23 that stores a program for determining whether the contents of this input pattern memory 22 are similar to any registered pattern stored in the registered pattern memory 21, and a CPU that executes the contents of this system program.
(Central processing unit) Consists of 24. And this
The CPU 24 is, for example, an 8-bit microprocessor, the system program memory 23 is composed of a ROM with a capacity of 2 Kbytes, and the input pattern memory 22 and the registered pattern memory 21 are RAMs with a capacity of 10 Kbytes. Composed by. Of this 10K bytes of RAM
1.75K bytes is used as input pattern memory 22.
Approximately 7.5 Kbytes is used as the registered pattern memory 21. The data extracted by the feature extraction section 2 is sent to the recognition processing section 3 having such a configuration as input pattern data and registered pattern data. First, a case where registered pattern data is sent will be described. When the registered pattern data is sent to the registered pattern memory 21 of the recognition processing section 3, as described above, the speaker registers several desired control contents in the speech recognition device by uttering the desired control contents. Here, now 1
Regarding the case where channel selection is stored as control content in the registered pattern memory 21,
The audio characteristic data of "1 channel" is extracted as digital data by the A/D converter 18. Then, this data is sent to the registered pattern memory 21 via the first I/O port 20, but at this time, it is temporarily stored in the input pattern memory 22 in the form of the determinant shown below. Here, the number of rows of the determinant is the number of samples, that is,
Indicates the number of times the output of the switched capacitor bandpass filter 16 is sampled in response to sample pulses at intervals of approximately 20 m _sec , and the number of columns is
The number of BPFs 16 is shown, and each component is a digitized sample value of each BPF. In this way, the extracted feature data of the speaker's voice has not yet been normalized to the amplitude information of the voice.
In other words, there is no processing to deal with the fact that the information on soft sounds is set back due to the position of the speaker's accent or strong sounds, and there is no processing to deal with the fact that the amplitude changes each time the same word is uttered. Therefore, it cannot be said that it adequately represents the characteristics of the speaker's voice. Therefore, the components of each row of the determinant are weighted. That is, the CPU 24 performs the following calculation stored in the system program 23 on the data once stored in the input pattern memory 22, represented by 〓 above, and the determinant 〓 of the calculation result is stored in the registered pattern memory 21. is stored as a registered pattern. In this way, the amplitude information of the audio information is normalized. This amplitude normalization is performed on all sounds uttered by the speaker as control content, and then the content (determinant) is stored in the registered pattern memory 21. In this way, when the speaker registers the desired control contents in the registered pattern memory 21 by utterance, the setting of the control contents for the speech recognition device is completed, and registration patterns of types equal to the number of control contents (〓 ₁ , 〓 ₂ ...〓
_o ) is stored in the registered pattern memory 21. As mentioned above, the calculation for normalizing the amplitude with respect to the determinant 〓 representing the characteristics of the voice is executed by the CPU 24 according to the program contents stored in the system program 23, but the execution contents are as follows. This is schematically explained below. That is, the first I/O port 2 in FIG.
0, the operations of the system program 23 and the CPU 24 can correspond to the functional operations shown in FIG. 3 below. In other words, the latch circuits 30 _{1 to 15} in FIG. 3 (actually, the determinant 〓
This corresponds to the part where one bag is stored. ) is latched with data corresponding to the determinant 〓, and the latched contents are supplied to an adder 31 and a multiplier 32, respectively. The output of this adder 31 is
The signal is supplied to the level determination circuit 33 and dividers 34 _{1 to 15} . The adder 31 adds the elements of each row component of the determinant 〓,

[Equation] is calculated, and each of the component elements latched in the latch circuits 30 _{1 to 15} is calculated by the sum of these values to the divider 34 _{1 to 15} .
divided by Here, multipliers 32 1 to 15 are provided before the dividers 34 _{1 to 15} and perform N multiplications, but this is to evaluate the division result in the integer part, and depending on the case, Can be omitted. Furthermore, the data whose amplitude has been normalized by being divided by the dividers 341 _{to 3415} is registered in the registered pattern memory 21 as a registered pattern through the bus line. Further, a predetermined level threshold is set in the level determination section 33, and when the level of the output of the adder 31 is below the set threshold, the latched contents of the latch circuits _{351 to 15} are Clear and
At other times, the two latch circuits are not controlled.
In this way, by causing the latch circuits _351-15 to perform the latch operation only when the output of the adder 31 is equal to or greater than a certain value, malfunctions due to noise when the detected voice is small can be prevented. As can be seen from the above explanation of FIG. It is stored in the pattern memory 22, and then the amplitude is normalized and registered as a characteristic pattern in the pattern memory 21.
is memorized. Next, a case will be described in which the speaker instructs the desired control content by voice with respect to the registered control content. When the speaker utters a desired control content among the registered control content and gives a voice command, the amplitude of the voice characteristic data is normalized and stored in the input pattern memory 22 in the same way as the registered pattern.
Here, it is assumed that an input pattern obtained by normalizing the amplitude of the content of the voice command given by the speaker is expressed by the following determinant 〓. This amplitude is normalized and input pattern memory 22
The input pattern 〓 stored in is referenced with the registered pattern already registered in the registered pattern memory 21 as the control content. By calculating the similarity between both patterns using this reference operation, it is determined that the control content corresponding to the pattern with the closest similarity is the control content commanded by the speaker. The degree of similarity between the input pattern and the registered pattern is determined by calculating the distance D between the patterns shown below. That is,
The determinant obtained by taking the absolute value of the difference of each component k _1j , f _1j between the registration pattern 〓 whose amplitude has been normalized and the input pattern 〓 is defined as the determinant distance pattern D representing the distance between both patterns. The similarity is calculated based on the summation value of each component of this determinant D. To further describe this, the distance pattern D is expressed by the following equation, and the similarity a is expressed as follows. The above calculation of the degree of similarity d is performed for all registered patterns, or in other words, patterns representing all control contents, and the pattern with the smallest value of degree of similarity d is the pattern commanded by the speaker by voice. It is determined that Speech recognition is performed in this way,
By normalizing the audio amplitude as described above, the misrecognition rate is significantly reduced. In this way, the speech recognition of the speaker's utterance is performed by calculating the degree of similarity between the registered pattern and the input pattern by the CPU 24 executing calculations instructed by the similarity calculation program set in the system program memory 23. This makes it possible to control devices using voice recognition. In speech recognition using the above-mentioned speech pattern matching method, the amplitude is normalized, so the information on the soft parts of the word is smaller than the strong parts of the word, and the amplitude fluctuates each time the same word is uttered. Misrecognition of speech due to easy-to-understand points is reduced. However, even if speakers utter the same word, the utterance times do not always match. To solve this problem, it is necessary to normalize the time axis as well, and next, this normalization of the time axis will be explained. The time axis is normalized by always dividing the time taken between the pronunciation start time and the pronunciation end time of a word pronounced by the speaker by a constant constant n.
In other words, if a speaker sometimes takes time T ₁ and sometimes takes time T ₂ to utter a certain word, in each case, the sample time interval for feature extraction is ΔT ₁ = T ₁ /n. , ΔT ₂ =T ₂ /n. This is based on the phenomenon that the times at which voice characteristics occur shift in response to shifts in the time axis. Therefore, it is necessary to detect the start time and end time of the speaker's utterance as accurately as possible. As mentioned above, extracting the speaker's voice features in both input patterns and registered patterns requires the following steps:
BPF16 _1~15 , sample/hold circuit 17 _1~1
5 , both circuits have time constant elements in their operation. In particular, the peak detection method of the sample-and-hold circuit greatly influences the correct detection of the end time of the speaker's utterance. Therefore, the sample configuring the feature extraction unit 2
The peak detection method and sampling timing in the hold circuit are important for accurately capturing the speaker's utterance length and normalizing the time axis. Next, another example of the feature extracting unit 2 suitable for making correction of the time axis will be described. Generally, when a speaker utters a certain single sound (voice waveform shown in FIG. 4), ripples with a pitch of P between peak values are obtained in the outputs of the BPFs _{161 to 15} , as shown in FIG. For example, the pitch P is approximately 8 m _sec when a single sound such as "a" is uttered, but in normal speech, this pitch falls within 5 to 15 m _sec . The outputs of the BPFs 16 _{1 to 15} shown in FIG.
As shown in the figure, peak detection is performed, but depending on the time constant during detection, as shown in Figure 4,
The end time of the utterance is incorrectly detected as shown in . In other words, when the time constant is increased to reduce ripples caused by peak detection, the detection output remains constant until time t ₂ , even though vocalization actually ends at time t ₁ , as shown in Figure 4. Recognizes that the audio is continuous. On the other hand, if the time constant is made small, ripples will occur in the detected waveform, making it impossible to expect accurate feature pattern extraction. This may affect the normalization of the time axis and the extraction of feature patterns, leading to incorrect speech recognition. Therefore, in recent years, methods have been considered in which peak value detection is performed at a cycle longer than the pitch cycle. This method will be explained below with reference to the drawings. FIG. 5 is a circuit block diagram showing another example of the feature extraction section ₃ shown in FIG.
Supplied to BPF41 _{1 to o} . And this BPF4
Each output of 11 _{to o} is connected to a diode D1 _{to o} and a sample/hold circuit 42 with a peak detection function.
Peak detection is performed by MOS transistors Q _{1 - o} forming MOS transistors Q _{1 - o} and capacitors C _{1 - o} holding the peak value. The peak values detected by peak detection, that is, the audio amplitude data are held in the capacitors C1 _-o , and these amplitude data are
Hex-decimal decoder 43 and MOS transistor
A _/
The signal is supplied to the D converter 45. Here, when the MOS transistors Q1 _-o are on, the MOS transistors _Q'1-o constituting the multiplexer 44 are off, and when one transistor group is on, the other transistor group is off. It is controlled so that Therefore, when the MOS transistors Q _{1 - o} are on, the audio amplitude data held in the capacitors C _{1 - o} is stored in the MOS transistors Q 1 - o when the MOS transistors Q _{1 - o} are off.
It is converted into a digital quantity which is supplied to the A/D converter 45 via Q' ₁ to o. The peak value is sampled for a time T longer than the pitch P described above.
When the peak value is held for a time T, the transistors T1 _~o , the resistors R1 _~o ,
The charges in the capacitors C1 _-o are discharged by a reset circuit 46 constituted by R'1 _-o . After this discharge time, detection of the peak value is started again and this is repeated until the end of the speaker's utterance. 6th
To explain this using a diagram, Figure 6 shows
It shows the output of one of BPF41 _{1 to o} , and the peak value of the voice is detected by the sampling pulse of time T shown in the figure, and the peak value is held.
With the reset pulse shown in the same figure, the capacitors C1 _~o
Since the charged charge is discharged, the A/D converter 45
The waveform shown in the figure is input to the input. 6th
As can be seen in the figure, the peak value of the voice is held for a time T longer than the pitch P mentioned above, and since the discharge is during the reset pulse period, the amplitude data of the detection output that is erroneous due to the discharge is transferred to the A/D converter 45. I don't even send it to. Next, the means for generating a sampling pulse for sample-holding the peak value for the time T mentioned above, and the means for generating a reset pulse will be explained using FIGS. 5, 7, and 8. A sampling pulse for sample-holding the peak value of the audio in the capacitors C1 _-o is obtained by the frequency divider 47 and the NAND gate 48. That is, a clock pulse indicated by CK in FIG. 7 is applied to the clock terminal CK of the frequency divider 48, and the clock pulse indicated by _CK in _FIG . The sampling pulse shown in Fig. 7 is obtained. This sampling pulse is applied to the MOS transistors Q1 _~o .
Controlling the conduction is as described above. Further, the first monomulti 49 detects the falling edge of the sampling pulse a, generates a pulse (FIG. 7), and inverts the output of the flip-flop 50 (FIG. 7). Then, Nand Gate 51,
The clock pulse CK' shown in FIG. 8 is applied to the m-bit counter 53 via the inverter 52, and the clock pulse CK' starts counting, and the binary-decimal decoder constituting the multiplexer 44 is sequentially switched, and all scanning is completed. The output Q of the m-bit counter 53 is supplied as a reset pulse to the flip-flop 50 via an inverter 54, and the state of the flip-flop 50 is inverted again. At the same time, the second monomulti 55 conducts the transistors T1 _-o to discharge the charges in the capacitors C1 _-o (this corresponds to in FIGS. 7, 8, and 6). occurs. An initialization circuit 57 connected to the frequency divider 47 is for resetting the frequency divider 47 when the power is turned on, and R is a resistor, D is a diode, and C is a capacitor. Further, the timing of reading data into the A/D converter 45 is determined by generating pulses shown in FIG. 8 in the following manner. As described above, at the rising edge of the sampling pulse (FIG. 7), the first monomulti 49 generates a pulse (FIGS. 7 and 8). This pulse inverts the state of the flip-flop 50 (FIGS. 7 and 8), and the m-bit counter 53 receives the clock pulse.
CK' (FIG. 8) is applied. The falling edge of this clock pulse (FIG. 8) is detected by the third monomulti 56, and the pulse shown in FIG. 8 is generated at the output of the third monomulti 56. Then, this pulse is transmitted to the A/D converter 45.
This is used as a data read timing pulse. In this way, in recent years, a time T larger than the above-mentioned pitch P observed when producing a single sound has been set as the sample time for extracting speech features, in order to prevent erroneous feature extraction during speech recognition due to ripples during peak detection. ing. Furthermore, when determining the end time of a speaker's utterance, the error range can be set to a range that is approximately smaller than the pitch length P, so that erroneous recognition can be reduced when normalizing with respect to the time axis. In other words, even if the time required for a speaker to produce the same word differs each time he/she utters the same word, misrecognition of speech due to this can be reduced. Next, the features of this invention will be explained. This invention was made in order to solve the above-mentioned erroneous recognition of speech caused by the presence of silent parts. Misrecognition caused by the presence of this silent portion will be explained using FIGS. 9 to 11.
FIG. 9 shows the time-frequency-level characteristics shown in FIG. 2 as changes in the level of each frequency component over time. Also the 10th
Figures a and b are simple depictions of BPF output data for one of the voice data for the numbers ``Hachi'' and ``Ichi'', respectively. Here, for convenience of explanation, the silent part of "ichi" is shown shorter than that of "hachi". Now, suppose that Figure 10 a and b are registered patterns, and a short voiceless part of the voice "Hachi" as shown in Figure 11 a is input. Compare this input pattern with the previously registered pattern. If you look at it, it will look like Figure 11 b and c. Figure 11b,
In c, the shaded part corresponds to the distance between the patterns,
FIG. 11b shows the distance of the input pattern "Hachi" to the registered pattern "Hachi", and FIG. 11C shows the distance of the input pattern "Hachi" to the registered pattern "Ichi". In this case, the 11th
The distance shown in Figure b is larger than that shown in Figure c, so even though the input voice is "Hachi",
It is recognized as “first”. In other words, even a change in the length of the silent portion may lead to erroneous recognition or non-recognition. Although this problem can be alleviated a little by normalizing the time axis as described above, it still remains a problem. Therefore, the present invention prevents input speech below a predetermined threshold value from being captured during the speaker's utterance period to prevent erroneous recognition or non-recognition due to variations in the length of the silent portion. One embodiment thereof will be explained using FIG. 1 and FIG. 12.
First, the case of registering control details will be explained. The feature data (corresponding to each row component of the above-mentioned determinant 〓) supplied to the input pattern memory 22 of the recognition processing unit 3 for each sampling period via the I/O port 20 is calculated for each row as described above. The components are added. If the result of this addition is greater than a predetermined threshold, that row is transferred to the registered pattern memory 21 with its amplitude normalized and stored at a predetermined address. On the other hand, if the addition result is smaller than a predetermined threshold value, the transfer to the registered pattern memory 21 is not performed. By the way, in the previous example, since the addresses of the registered pattern memory 21 are counted even for rows where the addition result is smaller than the predetermined threshold,
Rows for which the addition result is smaller than a predetermined threshold value are also eventually stored as "0" data at the corresponding address in the registered pattern memory. In contrast, in the present invention, addresses in the registered pattern memory 21 are not counted for rows for which the addition result is smaller than a predetermined threshold.
To further explain this, if the addition result is smaller than a predetermined threshold, addresses are not counted as described above, and the address corresponding to the row immediately before the row for which the addition result is smaller than the predetermined threshold remains specified. It's summery. From this state, when the addition result becomes larger than the predetermined threshold again, the address count advances, and the normalized row component of the amplitude at this time is
The normalized amplitude of the row immediately before the row for which the addition result is smaller than a predetermined threshold is stored at the address immediately following the stored address. Therefore, even if a "hachi" signal containing a silent part as shown in FIG. Registered on 21. Furthermore, even if a signal "Ichi" including a silent part as shown in FIG. The same is true when a speaker commands a desired control content among the registered control content by vocalization, and if the addition result of the components of a certain row is smaller than a predetermined threshold, the input pattern memory 22 is Counting of addresses stops. If there is a part where the amplitude level is smaller than a predetermined threshold during the speaker's utterance period, by not registering this part as data, it is possible to Erroneous recognition or non-recognition due to variations in the length of the silent portion as described above can be prevented. A program for performing the above-mentioned processing is stored in the system program memory 23, and is executed by the OPU 24 in accordance with this program, and the content of the execution will be schematically explained next. That is, the first I/D port 2 in FIG.
0, the operations of the system program 23 and the CPU 24 can correspond to the functional operations described using the following FIGS. 13 and 16. In the speech recognition device shown in FIG. 13, the circuit for normalizing the time axis is substantially the same as the circuit shown in FIG. 5, so the same reference numerals are given and detailed explanation will be omitted. On the other hand, the amplitude normalization is different from the above example. That is, the above-mentioned amplitude normalization means calculates the sum of the peak values of the outputs of a plurality of BPFs at each sample time,
The peak value of the output of each BPF at the sample time is divided by this total to obtain the ratio of the peak value of each BPF to the total, and this is registered or used as an input pattern. On the other hand, in the apparatus shown in Fig. 13, the maximum value of the output peak values of each BPF is selected for each sample time, and the peak value of each BPF at that sample time is divided by this maximum peak value. The ratio of the peak value of the output of each BPF to the maximum peak value is determined, and this is registered or used as an input pattern. Therefore, before entering into a description of the features of the present invention, the amplitude normalization means in the apparatus shown in FIG. 13 will be described with reference to FIGS. 14 and 15. In addition, in Fig. 14, CK, Q ₀ , Q ₁ , ,
, are the same as the signals shown as CK, Q ₀ , Q ₁ , . . . in FIG. 7 in the operation description of FIG. 5 above. Also, Fig. 15 CK′,,
The signals shown in , , , are also shown as CK′, , , in FIG. 8 in the operation explanation of FIG.
, is the same as the signal shown as . The signal shown in FIG. 15 indicates the conversion end signal of the A/D converter 45. That is, the data indicating the peak value of the audio held in the capacitors C1 _{-o shown} in FIG. is supplied to the A/D converter 45, and the monomulti 5
The data is converted into a digital quantity at the timing of the data read timing pulse (FIG. 15) generated from 6. The A/D converter 45 generates a conversion completion signal shown in FIG. 15 each time it completes A/D conversion of the data held in each capacitor C1 _-o . Further, the output signal of the monomulti 55 shown in FIG.
The signal shown as in the figure is derived. Similarly, the output signal of the monomulti 57 is supplied to a fifth monomulti 58 to obtain the signals shown in FIGS. 14 and 15. The output signal of this monomulti 58 is used as a reset pulse to discharge the charges in the capacitors C1 _-o . The output of the A/D converter 45 is connected to a latch circuit 59.
Supplied from _{1 to o} . The write timing of the latch circuits 591 _-o is obtained by the output of the AND circuits _601-o . That is, this AND circuit 60
The above-mentioned conversion end signal (FIG. 15) is supplied to one input terminal of each of 1 _{to o} , and the output of the binary-decimal decoder 43 is supplied to the other input terminal, respectively. . Therefore, AND circuits 60 _{1 to 60} open their gates in sequence at the timing of the conversion end signal,
The output is supplied as a clock pulse to the corresponding latch circuit _591-o , and the output of the A/D converter 45 is sequentially written to the corresponding latch circuit 591 _-o . Each row component of the data determinant 〓 latched in the latch circuits 59 _{1 to 59} is connected to a multiplier 61 ₁ .
_~o is multiplied by N and supplied to dividers 621 _~o . Then, in the dividers 61 _{1 to 61 o} , the maximum peak value of the audio peak values at each sampling time sampled and held in the capacitors C _{1 to o} is divided by a value obtained by converting the maximum peak value into a digital quantity. The outputs of divider 61 _{1 to o} that have undergone division processing are sent to latch circuit 6
3 Written in _1~o . The output signal of the monomulti 55 (FIG. 15) is used as the timing signal for this writing. On the other hand, the data written in the latch circuits 59 _{1 to 59 o} are added to an adder 65 and supplied to a level determination circuit 66 . This level determination circuit 66 outputs the output of the adder 65 (

When the level (corresponding to [formula]) is below a predetermined threshold, the latch circuit 6
3 Clear the contents latched in _{1 to o} . In this case, the output of the level determination circuit 66 and the output of the monomulti 67 (same timing as shown in FIG. ₁₅ ) are supplied to the clear terminals of the latch circuits 631 to 63o via the AND circuit 68, and the latch circuits 63 _1～o
is cleared at the timing of the output of the monomulti 67. When the output level of the adder 65 is higher than a predetermined threshold, the contents latched in the latch circuits 63 _{1 to 63 o} are not cleared, and the contents of the address counter 8, the details of which will be described later, are cleared.
The input pattern memory 61 (actually corresponds to the part of the input pattern memory that stores the input pattern) is connected to the input pattern memory 61 through the bus line at the timing of the output of step 4.
is memorized. Here, a means for determining the maximum peak value among the peak values of audio in each sample period will be explained. This includes latch circuit 69 and latch circuit 7.
0, comparator 71, NOR circuits 72, 73, data select gate 74, inverter circuits 75, 76,
This is done by a circuit consisting of an OR circuit 77. That is, n pieces of converted data from the A/D converter 45 are sequentially supplied to either one of the latch circuits 69 and 70. The contents X ₁ and X ₂ latched in the latch circuits 69 and 70 are compared in size by a comparator 71, and if X ₁ < X ₂ , the output becomes "H", and if X ₁ = X ₂ , the output becomes “H”, and X ₁ > X ₂
Then the output becomes "H". The NOR circuit 72 is supplied with the output and a conversion end signal of the A/D converter 45 inverted by an inverter circuit 76 . The output and the output of the inverter circuit 76 are supplied to the NOR circuit 73. Noah circuit 7
Depending on the output state of the comparator 71, either one of the latch circuits 2 and 73 becomes "H", making it possible to write converted data into the corresponding latch circuits 70 and 69. In the data select gate 74, latch circuits 69 and 7 are connected according to the output of the comparator 71.
Data latched to one of the zeros is selected and supplied to dividers 621 _-o . That is, if the output is "H", data X ₂ is selected,
If the output is "L", data _X2 is selected. Note that if X ₁ =X ₂ , either one may be selected, but in this configuration, data X ₁ is selected. The latch circuits 69 and 70 are cleared by the initialization circuit 5.
7 is inverted by an inverter circuit 75 and the output of the monomulti 58 is generated by a signal passed through an OR circuit 77. The output signal of the OR circuit 77 is shown in FIG. For example, if the power of the device is turned on at the timing of the pulse 〓 of these signals, the OR circuit 77 causes the pulse 〓 to be applied to the latch circuit 6.
9 and 70, and the latch circuits 69 and 70 are in a clear state. Therefore, the output of the comparator 71 becomes "H", and the output becomes "L". At this time, when the A/D converter 45 operates, only the output of the NOR circuit 72 becomes "H" at the timing of the first conversion end signal, and the first converted data is written into the latch circuit 70. As a result, the output of the comparator 71 becomes "H", and the output becomes "L". Therefore, at the timing of the second conversion end signal, the output of the NOR circuit 73 becomes "H" and the second conversion data is transferred to the latch circuit 6.
9 is written. Thereafter, in the same way, one of the comparators 71 becomes "H" depending on the magnitudes of the outputs X ₁ and X ₂ of the latch circuits 69 and 70, and the output of the NOR whose output becomes "H" Conversion data is written into the latch circuit 70 or 69 corresponding to the circuit 72 or 73. In this way, the larger data of the latch data of the latch circuits 70 and 69 is supplied to the dividers 621 _-o via the data select gate 74. Therefore, in the dividers 621 _-o , data obtained by dividing each peak value of the audio in the first sample period by the maximum peak value of that period is finally obtained and written into the latch circuits _631-o . When the amplitude normalization for each peak value in the first sample period is completed, the latch circuits 69 and 70 send the output signal of the monomulti 58 (FIGS. 11 and 12).
is reset and returns to the initial state. Thereafter, the amplitude is normalized for the peak value data obtained in the second and subsequent sampling periods in the same manner. Next, referring to the signal waveform diagram of FIG. 16, a description will be given of a prohibition means for preventing input audio from inputting an amplitude level portion below a predetermined threshold value, which is a feature of the present invention. In addition, in Fig. 16, the signals shown in , , in Fig. 15 above are
This is the same signal as shown in . When a speaker inputs audio into the device by speaking, the latch circuits 59 _{1 to 59} are activated at each sample time as described above.
The peak value converted to a digital quantity is latched. If the addition result of the latched peak values is larger than the threshold of the level determination circuit 66, the amplitude normalized data is stored in the input pattern memory 66.
will be stored in. Therefore, assuming that the output of the adder circuit 65 exceeds the threshold of the level determination circuit 66, the output of the level determination circuit 66 becomes low level as described above. The output of this level determination circuit 68 is supplied to the AND circuit 68 as described above, and further supplied to the AND circuit 79 via the inverter circuit 78. The AND circuit 79 is also supplied with the output signal of the monomulti 67. Therefore, the signal shown in FIG. 16 is obtained from the AND circuit 79 at the timing of the output signal of the monomulti 67. The output of the AND circuit 79 is supplied as a reset pulse to the counter 81 via the OR circuit 80, thereby placing the counter 81 in a reset state. Further, the output of the AND circuit 68 is supplied to an AND circuit 83 via an inverter circuit 82. This AND circuit 83 is also connected to the output signal of the monomulti 58 (the 16th
Figure) is supplied. Therefore, AND circuit 83
The signal shown in FIG. 16 is obtained at the output of the monomulti 58 at the timing of the output signal. The output of this AND circuit 83 is supplied to an address counter 84 as a clock pulse. As a result, the count value of the address counter 84 is incremented by one each time one clock pulse is supplied, and the count value of the address counter 84 is incremented by one each time one clock pulse is supplied.
3 Write the data latched in ₁ to o to a predetermined address in the input pattern memory 64. Also,
The output of the AND circuit 83 is further connected to the flip-flop 8
5. This causes flip-flop 8
The output of 5 is sent to an AND circuit 8 as shown in FIG.
is inverted by the first output pulse of 3,
It becomes “L” level. This flip-flop 85
The output of is supplied to a NOR circuit 86. In this state, when the output level of the adder circuit 65 becomes smaller than the threshold value of the level determination circuit 66, the signal shown in FIG. 16 is obtained at the output of the AND circuit 68. As a result, the latch circuits 631 _-o are brought into the reset state as described above. Further, the output of the AND circuit 68 is inverted by an inverter circuit 82 and supplied to the NOR circuit 86. As a result, the gate of the NOR circuit 86 is opened at the timing of the signal shown in FIG. 16, and its output is supplied to the counter 81 as a clock pulse. At this time, since the output of the AND circuit 83 is not obtained, the address counter 84 of the input pattern memory 64 stops counting. Therefore, address counter 8
The address of the input pattern memory 64 designated by the output of No. 4 is not moved and is held at the address immediately before the output of the adder circuit 65 becomes equal to or less than the threshold value of the level determination circuit 66. By the way, if the output of the adder circuit 64 again exceeds the threshold of the level determination circuit 65 before the eighth clock pulse is supplied, the counter 81 outputs the output signal of the AND circuit 79 (the 16th clock pulse).
(Figure). At this time, an output signal (FIG. 16) is also obtained from the AND circuit 83, the count value of the address counter 84 is incremented by one, and the addition result of the addition circuit 65 as described above becomes the threshold value of the level determination circuit 66. The address following the previous address is specified, and the data is stored here. Conversely, even if eight clock pulses are supplied, if the addition result of the adder circuit 65 does not exceed the threshold of the level judgment circuit 66, the _Q3 output of the counter 81 (Fig. 16) will be output at the timing of the eighth clock pulse. It becomes “H”. This Q ₃ output is supplied to the flip-flop 50 via an inverter circuit 87 to reset it, and is also supplied to a seventh monomulti 88. As a result, the monomulti 88 derives the signal _P1 shown in FIG.
This signal is used as a processing start signal. That is, when this processing start signal _P1 is derived, the recognition processing unit 3 determines that all the sounds uttered by the speaker have been stored as input patterns in the input pattern memory 64, and compares the registered pattern with the input pattern. Perform comparison processing. Note that the figure does not show the part that performs this comparison process. When this comparison processing operation is completed, a processing end signal shown in FIG. 16 is derived, and the counter 81 is reset. Further, this processing end signal is supplied to the flip-flop 85 as a set pulse to set the flip-flop 85 to a set state, that is, to an output "H" state, and to the address counter 84 and the input pattern memory 6 via an OR circuit 89.
4 as a reset pulse to put them in the reset state. Thereafter, the above-described operations are repeated every time a voice is input. Note that when the device is powered on, the flip-flop 85 transfers the output of the initialization circuit 57 to the inverter circuit 75.
The set state is set by the inverted signal. At this time, the counter 81 is reset by the signal that passes the output of the inverter circuit 75 through the OR circuit 80, and the address counter 84 and input pattern memory 64 use the signal that passes the output of the inverter circuit 75 through the OR circuit 89. The reset state is set by . In this way, when the addition result of the adder circuit 64 is smaller than the threshold value of the level judgment circuit 66, the counting operation of the address counter 84 is stopped, and the input pattern memory 64 stores the address immediately before the addition result becomes smaller than the threshold value of the level judgment circuit 66. remains specified. If this state lasts for only a period shorter than the period in which eight clock pulses are counted by the counter 81 (corresponding to eight sampling times), the addition result of the adder circuit 65 is added to the level judgment circuit 66. When the value exceeds the threshold, the address counter 84 starts counting again, and data is loaded into the input pattern memory. Conversely, the above state is the counter 81
If it lasts for a period shorter than the period in which eight clock pulses are counted by , it is assumed that all data have been input, and the input pattern and the registered pattern are compared. In the above description, the present invention has been described based on the case where the speaker commands the desired control content by vocalization with respect to the control content that has been registered in advance.
When registering a plurality of control contents, data is written to the registered pattern memory in the same manner. Note that the device to be controlled by the voice recognition device according to the present invention is not limited to television receivers, but can be applied to general systems that require remote control. As described above, according to the present invention, it is possible to provide a speech recognition device that can solve the problem of misrecognition of speech particularly caused by the presence of silent parts.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an example of what is currently being considered as a speech recognition device and an embodiment of the present invention, and FIGS. 2 and 3 are provided to explain what is currently being considered as a speech recognition device. A time-frequency-amplitude level characteristic diagram and a circuit block diagram; Fig. 4 is a signal waveform diagram used to explain the detection characteristics of speech waves; Fig. 5 shows another example of what is currently being considered as a speech recognition device. 6 is a signal waveform diagram to explain the operation of FIG. 5, FIGS. 7 and 8 are timing charts to explain the operation of FIG. 5, and FIG. FIGS. 10 to 12 are time-frequency-level characteristic diagrams used to explain the invention. FIGS. 10 to 12 are schematic signal waveform diagrams used to explain the invention. FIG. A circuit block diagram showing an example, and FIGS. 14 to 16 are timing charts for explaining the operation of FIG. 13. 21...Registered pattern memory, 22...Input pattern memory, 23...System program memory, 24...CPU, 55 to 58, 67, 88
...Monomulti, 68,79,83...AND circuit, 75,78,82,87...Inverter circuit, 80,89...OR circuit, 81...Counter, 84...Address counter, 85...Flip-flop , 86...Noah circuit.

Claims (1)

[Claims] 1 A plurality of filters each extracting components in different frequency bands from the voice uttered by a speaker, the outputs of the plurality of filters are sampled at the same timing, the peak value of the output of each filter is detected during the sampling period, and the peak value of the output of each filter is detected. peak value detection means that repeatedly performs an operation of holding the peak value for the sampling period at predetermined time intervals during the utterance period of the speaker; and outputs of the plurality of filters during the plurality of sampling periods in the peak value detection means. at least a recognition processing section having a prohibition means for prohibiting the peak value of a sampling period in which the peak value of A speech recognition device characterized in that only peak values of outputs of a plurality of filters during a sampling period are used as data indicating characteristics of speech uttered by a speaker.