JPS61229367A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS61229367A
JPS61229367A JP60071470A JP7147085A JPS61229367A JP S61229367 A JPS61229367 A JP S61229367A JP 60071470 A JP60071470 A JP 60071470A JP 7147085 A JP7147085 A JP 7147085A JP S61229367 A JPS61229367 A JP S61229367A
Authority
JP
Japan
Prior art keywords
region
impurity concentration
well
channel region
impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60071470A
Other languages
Japanese (ja)
Inventor
Kiyoshi Nishimura
清 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP60071470A priority Critical patent/JPS61229367A/en
Publication of JPS61229367A publication Critical patent/JPS61229367A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213Channel regions of field-effect devices
    • H10D62/221Channel regions of field-effect devices of FETs
    • H10D62/235Channel regions of field-effect devices of FETs of IGFETs

Abstract

PURPOSE:To set the desired electric characteristics by making the impurity concentration of the channel region set in the conductive region differ from that of other conduction regions than the channel region. CONSTITUTION:On the surface of the semiconductor substrate 20 the resist film 40 is formed to cover the surface, and the aperture 42 to diffuse impurity is formed on the film 40. From the aperture 42 the impurity like boron, etc. is diffused. As to the condition of impurity diffusion, the impurity concentration decreases in accordance with the distance from the aperture 42. After the P well 22 is formed in this way by locally controlling the impurity concentration, the source region 26 and the drain region 28 are installed in the P well 22 in the manner wherein the region where the specified impurity concentration is obtained becomes the drain region 28.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、たとえば、MO3電界効果トランジスタな
どの半導体装置およびその製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device such as an MO3 field effect transistor, and a method for manufacturing the same.

〔従来の技術〕[Conventional technology]

一般に、電界効果トランジスタは、第7図および第8図
に示すように、N型シリコンなどの一導電型の半導体基
板2に反対導電型の導電領域としてのpウェル(wel
l) 4が形成され、このpウェル4には、一定の間隔
を置いてpウェル4とは反対導電型のソース領域6およ
びドレイン領域8が形成され、これらソース領域6およ
びドレイン領域8の間にはチャンネル領域工0が形成さ
れている。
Generally, as shown in FIGS. 7 and 8, a field effect transistor includes a semiconductor substrate 2 of one conductivity type, such as N-type silicon, and a p-well (well) as a conductive region of the opposite conductivity type.
l) 4 is formed, and in this p-well 4, a source region 6 and a drain region 8 of the opposite conductivity type to that of the p-well 4 are formed at regular intervals, and between these source region 6 and drain region 8, A channel region pattern 0 is formed in the area.

半導体基板2、pウェル4、ソース領域6およびドレイ
ン領域8の表面は、酸化膜12で覆われているとともに
、ソース領域6およびドレイン領域8の表面にはソース
電極14、ドレイン電極16が形成され、チャンネル領
域10を覆う酸化膜13は他の部分より薄く設定され、
この薄い酸化J[13の表面には、アルミニウムなどの
蒸着によってゲート電極18が形成されている。
The surfaces of the semiconductor substrate 2, p-well 4, source region 6, and drain region 8 are covered with an oxide film 12, and a source electrode 14 and a drain electrode 16 are formed on the surfaces of the source region 6 and drain region 8. , the oxide film 13 covering the channel region 10 is set thinner than other parts,
A gate electrode 18 is formed on the surface of this thin oxide J[13 by vapor deposition of aluminum or the like.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来より、このような電界効果トランジスタでは、半導
体基板2の表面に、ソース領域6、ドレイン領域8およ
びチャンネル領域10を形成する部分を考慮することな
く、無差別に不純物の拡散またはイオン注入を行ってp
ウェル4を形成しているので、pウェル4の中心および
その表面層が最も高い不純物濃度となり、その平面方向
および深さ方向に濃度勾配を呈する。すなわち、チャン
ネル領域10の不純物濃度もソース領域6およびドレイ
ン領域8の近傍の不純物濃度も均一なプロファイルとな
っている。
Conventionally, in such a field effect transistor, impurities are diffused or ion-implanted indiscriminately into the surface of the semiconductor substrate 2 without considering the portions where the source region 6, drain region 8, and channel region 10 are to be formed. Tep
Since the well 4 is formed, the center of the p-well 4 and its surface layer have the highest impurity concentration, and a concentration gradient is exhibited in the plane direction and the depth direction. That is, the impurity concentration of the channel region 10 and the impurity concentrations near the source region 6 and drain region 8 have a uniform profile.

このため、この種の電界効果トランジスタでは、周波数
特性、耐圧、閾値電圧V?Hなどの電気的特性が固定し
、これらの特性を任意に設定することが困難であり、特
性の異なるデバイスを同一半導体基板上に任意に形成す
ることができなかった。
For this reason, this type of field effect transistor has frequency characteristics, breakdown voltage, and threshold voltage V? Electrical characteristics such as H are fixed, making it difficult to arbitrarily set these characteristics, and it has been impossible to arbitrarily form devices with different characteristics on the same semiconductor substrate.

そこで、この発明は、周波数特性、耐圧、闇値電圧など
の電気的特性を任意に設定可能な半導体装置およびその
製造方法の提供を目的とする。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device in which electrical characteristics such as frequency characteristics, withstand voltage, and dark voltage can be arbitrarily set, and a method for manufacturing the same.

〔問題点を解決するための手段〕[Means for solving problems]

この発明を第1図ないし第6図に示した実施例を参照し
て説明する。
This invention will be explained with reference to the embodiments shown in FIGS. 1 to 6.

この発明の半導体装置は、一導電型の半導体基板20に
設置した反対導電型の導電領域(pウェル22)に、ソ
ース領域26およびドレイン領域28を設置し、これら
ソース領域26およびドレイン領域28の間に形成され
たチャンネル領域24にゲートを臨ませてなる半導体装
置において、導電領域(pウェル22)に設定される前
記チャンネル領域24の不純物濃度をチャンネル領域を
除く他の導電領域の不純物濃度と異ならせてなるもので
ある。
In the semiconductor device of the present invention, a source region 26 and a drain region 28 are provided in a conductive region (p well 22) of an opposite conductivity type provided in a semiconductor substrate 20 of one conductivity type. In a semiconductor device in which a gate faces a channel region 24 formed in between, the impurity concentration of the channel region 24 set in the conductive region (p well 22) is compared with the impurity concentration of other conductive regions other than the channel region. They are different.

また、この発明の半導体装置の製造方法は、半導体基板
20にチャンネル領域24となる部分を遮蔽して不純物
の拡散またはイオン注入により半導体基板とは反対導電
型の導電領域を形成し、チャンネル領域24の不純物濃
度を低く制御する。
Further, in the method of manufacturing a semiconductor device of the present invention, a conductive region having a conductivity type opposite to that of the semiconductor substrate is formed by shielding a portion of the semiconductor substrate 20 that will become the channel region 24 by diffusion of impurities or ion implantation, and Control the impurity concentration low.

〔作   用〕[For production]

この発明の半導体装置は、チャンネル領域24の不純物
濃度をチャンネル領域24を除く部分の導電領域のそれ
より低くして不純物濃度分布を異ならせ、導電領域の周
辺部の拡散プロファイルの電界効果によって周波数特性
、耐圧、闇値電圧などの電気的特性が任意に設定される
In the semiconductor device of the present invention, the impurity concentration of the channel region 24 is made lower than that of the conductive region excluding the channel region 24 to make the impurity concentration distribution different, and the frequency characteristics are determined by the electric field effect of the diffusion profile in the peripheral portion of the conductive region. , electrical characteristics such as withstand voltage and dark value voltage are arbitrarily set.

また、この発明の半導体装置の製造方法は、チャンネル
領域を形成すべき部分以外の部分から不純物を拡散し、
あるいは、イオン注入を行い、チャンネル領域に設定す
る導電領域の不純物濃度を少なくしている。
Further, the method for manufacturing a semiconductor device of the present invention includes diffusing impurities from a portion other than a portion where a channel region is to be formed;
Alternatively, ion implantation is performed to reduce the impurity concentration of the conductive region set in the channel region.

〔実 施 例〕〔Example〕

以下、この発明の実施例を図面を参照して詳細に説明す
る。
Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図および第2図は、この発明の半導体装置の実施例
を示し、第1図はその平面構造、第2図はその■−■線
に沿う断面を表している。
1 and 2 show an embodiment of the semiconductor device of the present invention, with FIG. 1 showing its planar structure, and FIG. 2 showing its cross section along the line ■-■.

第1図および第2図において、N型シリコンなどの一導
電型の半導体基板20に反対導電型の導電領域としての
pウェル22が形成されている。
1 and 2, a p-well 22 as a conductive region of the opposite conductivity type is formed in a semiconductor substrate 20 of one conductivity type such as N-type silicon.

この実施例では、このpウェル22のほぼ中心領域に、
不純物濃度が低い部分をチャンネル領域24としてpウ
ェル22とは反対導電型のソース領域26およびドレイ
ン領域28が形成されている。
In this embodiment, approximately in the central region of this p-well 22,
A source region 26 and a drain region 28 of a conductivity type opposite to that of the p-well 22 are formed using a portion with a low impurity concentration as a channel region 24 .

半導体基板20、pウェル22、ソース領域26および
ドレイン領域28の表面は、′酸化膜30で覆われてい
るとともに、ソース領域26およびドレイン領域28の
表面にはソース電極32、ドレイン電極34が形成され
ている。
The surfaces of the semiconductor substrate 20, the p-well 22, the source region 26, and the drain region 28 are covered with an oxide film 30, and a source electrode 32 and a drain electrode 34 are formed on the surfaces of the source region 26 and drain region 28. has been done.

そして、チャンネル領域24を覆う酸化膜36は、他の
部分より薄く設定され、その表面にはアルミニウムなど
の蒸着によってゲート電極38が形成されている。
The oxide film 36 covering the channel region 24 is set thinner than other parts, and a gate electrode 38 is formed on its surface by vapor deposition of aluminum or the like.

このようにpウェル22を構成する導電領域の不純物濃
度勾配をチャンネル領域24と他の領域とで異ならせ、
たとえば、チャンネル領域24の不純物濃度を少なくす
ることにより、それに応じた周波数特性、ダイナミック
耐圧、スタティック耐圧、閾値電圧vT□などの電気的
特性を得ることができる。
In this way, the impurity concentration gradient of the conductive region constituting the p-well 22 is made different between the channel region 24 and other regions,
For example, by reducing the impurity concentration of the channel region 24, electrical characteristics such as frequency characteristics, dynamic breakdown voltage, static breakdown voltage, and threshold voltage vT□ can be obtained.

また、pウェル22は、第3図に示すように、その周縁
部がチャンネル領域24の中央部に位置するようにして
もよい。このようにすれば、pウェル22の不純物濃度
の低い部分をチャンネル領域24に設定でき、闇値電圧
VTHなどの電気的特性を変更できる。
Furthermore, as shown in FIG. 3, the p-well 22 may have its peripheral edge located in the center of the channel region 24. In this way, a portion of the p-well 22 with a low impurity concentration can be set as the channel region 24, and electrical characteristics such as the dark voltage VTH can be changed.

第4図ないし第6図はこの発明の半導体装置の製造方法
の実施例を示している。
4 to 6 show an embodiment of the method for manufacturing a semiconductor device according to the present invention.

この実施例は、pウェル22を不純物の拡散によって形
成する場合を示しており、第4図に示すように、半導体
基板20の表面にレジスト膜40を形成してその表面を
覆うとともに、レジスト膜40に選択的に不純物拡散用
の開口42を形成する。この場合、チャンネル領域24
となる部分は、レジスト膜40で覆い、その周辺部に開
口42を形成し、ボロンなどの不純物を拡散する。
This embodiment shows the case where the p-well 22 is formed by diffusion of impurities, and as shown in FIG. 4, a resist film 40 is formed on the surface of the semiconductor substrate 20 to cover the surface, and the resist film An opening 42 for impurity diffusion is selectively formed in 40 . In this case, the channel area 24
The portion to be formed is covered with a resist film 40, an opening 42 is formed around the resist film 40, and an impurity such as boron is diffused.

不純物の拡散状態は、第5図に示すように、開口42か
ら遠ざかるに従って不純物濃度が低下する。この場合、
pウェル22の周縁部は両側の開口42から拡散される
不純物同士が重なるが、開口42から遠(なるに従って
不純物濃度が低下するので、チャンネル領域24となる
部分の不純物濃度は、開口42の直下より低下したもの
になるとともに、不純物の拡散量および開口42の位置
によってチャンネル領域となる部分の不純物濃度を制御
することができる。
Regarding the diffusion state of impurities, as shown in FIG. 5, the impurity concentration decreases as the distance from the opening 42 increases. in this case,
The impurities diffused from the openings 42 on both sides overlap the peripheral edge of the p-well 22, but the impurity concentration decreases as the distance from the opening 42 increases, so the impurity concentration of the portion that will become the channel region 24 is directly below the opening 42. In addition to further reducing the impurity concentration, the impurity concentration in the portion that will become the channel region can be controlled by the amount of impurity diffusion and the position of the opening 42.

たとえば、第6図に示すように、チャンネル領域となる
部分に、pウェル22の不純物濃度が最も低くなる周縁
部を設定することができる。
For example, as shown in FIG. 6, a peripheral portion where the impurity concentration of the p-well 22 is lowest can be set in a portion that will become a channel region.

このようにpウェル22を局部的に不純物濃度を制御し
て形成した後、特定の不純物濃度が得られている領域が
チャンネル領域24となるように、そのpウェル22に
ソース領域26およびドレイン領域28を設置する。
After forming the p-well 22 by controlling the impurity concentration locally in this way, a source region 26 and a drain region are formed in the p-well 22 so that the region where a specific impurity concentration is obtained becomes the channel region 24. Install 28.

そして、半導体基板20、pウェル22、ソース領域2
6およびドレイン領域28の表面に形成された酸化膜3
0のソース領域26およびドレイン領域28にそれぞれ
ソース電極32、ドレイン電極34を形成するとともに
、チャンネル領域24を覆う酸化膜36の表面にゲート
電極38を形成する。
Then, a semiconductor substrate 20, a p-well 22, a source region 2
6 and the oxide film 3 formed on the surface of the drain region 28
A source electrode 32 and a drain electrode 34 are formed in the source region 26 and drain region 28 of 0, respectively, and a gate electrode 38 is formed on the surface of the oxide film 36 covering the channel region 24.

したがって、このような製造方法によれば、pウェル2
2のチャンネル領域24に設定される部分の不純物濃度
を制御でき、このような制御眸、同一の半導体基板上の
所望の位置で部分的に行うことができ、pウェル22の
周辺部の拡散プロファイルの電界効果および不純物濃度
を利用して電気的特性を改善した半導体装置を得ること
ができる。
Therefore, according to such a manufacturing method, the p-well 2
The impurity concentration of the portion set in the channel region 24 of 2 can be controlled, and such control can be performed partially at a desired position on the same semiconductor substrate, and the diffusion profile of the peripheral portion of the p well 22 can be controlled. A semiconductor device with improved electrical characteristics can be obtained by utilizing the field effect and impurity concentration.

なお、この実施例ではpウェル22を不純物拡散によっ
て形成したが、イオン注入によって形成してもよい。
Although the p-well 22 is formed by impurity diffusion in this embodiment, it may also be formed by ion implantation.

また、実施例では、N型の半導体基板にpウェルを形成
した場合について説明したが、この発明は、P型の半導
体基板にnウェルを形成する場合にも同様に提供できる
Furthermore, in the embodiment, a case has been described in which a p-well is formed in an N-type semiconductor substrate, but the present invention can be similarly provided in a case in which an n-well is formed in a P-type semiconductor substrate.

また、ゲート電極38は、実施例のようにメタルで構成
してもよく、また、ポリシリコンで構成してもよい。
Further, the gate electrode 38 may be made of metal as in the embodiment, or may be made of polysilicon.

〔発明の効果〕〔Effect of the invention〕

° 以上説明したように、この発明の半導体装置によれ
ば、チャンネル領域の不純物濃度の制御によって周波数
特性、闇値電圧、ダイナミック耐圧、スタティック耐圧
など所望の電気的特性を設定でき、しかも、同一半導体
基板上に異なる特性を設定することができる。
° As explained above, according to the semiconductor device of the present invention, desired electrical characteristics such as frequency characteristics, dark voltage, dynamic breakdown voltage, and static breakdown voltage can be set by controlling the impurity concentration of the channel region, and moreover, Different properties can be set on the substrate.

また、この発明の半導体装置の製造方法によれば、チャ
ンネル領域の不純物濃度を任意に制御することができ、
所望の特性を持つ半導体装置を容易に製造することがで
きる。
Further, according to the method of manufacturing a semiconductor device of the present invention, the impurity concentration of the channel region can be arbitrarily controlled.
A semiconductor device having desired characteristics can be easily manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の半導体装置の実施例の平面構造を示
す説明図、第2図は第1図のn−n線に沿う断面図、第
3図はこの発明の半導体装置の他の実施例を示す断面図
、第4図は半導体基板に設置したレジスト膜およびその
開口を示す平面図、第5図は不純物拡散の状況を示す断
面図、第6図は不純物拡散の他の実施例を示す断面図、
第7図は一般的な電界効果トランジスタの電極配置を示
す平面図、第8図は第7図の■−■線に沿う断面図であ
る。 20・・・半導体基板、22・・・導電領域としてのp
ウェル、24・・・チャンネル領域、26・・・ソース
領域、28・・・ドレイン領域。 第3図 第4図 第5図 第7図 第8図
FIG. 1 is an explanatory diagram showing a planar structure of an embodiment of the semiconductor device of the present invention, FIG. 2 is a sectional view taken along line nn in FIG. 1, and FIG. 3 is another embodiment of the semiconductor device of the present invention. 4 is a plan view showing a resist film installed on a semiconductor substrate and its opening, FIG. 5 is a sectional view showing the state of impurity diffusion, and FIG. 6 is another example of impurity diffusion. A cross-sectional view showing,
FIG. 7 is a plan view showing the electrode arrangement of a general field effect transistor, and FIG. 8 is a cross-sectional view taken along the line ■--■ in FIG. 20...Semiconductor substrate, 22...P as a conductive region
Well, 24... Channel region, 26... Source region, 28... Drain region. Figure 3 Figure 4 Figure 5 Figure 7 Figure 8

Claims (2)

【特許請求の範囲】[Claims] (1)一導電型の半導体基板に設置した反対導電型の導
電領域に、ソース領域およびドレイン領域を設置し、こ
れらソース領域およびドレイン領域の間に形成されたチ
ャンネル領域にゲートを臨ませてなる半導体装置におい
て、前記導電領域に設定される前記チャンネル領域の不
純物濃度をチャンネル領域を除く導電領域の不純物濃度
より異ならせてなることを特徴とする半導体装置。
(1) A source region and a drain region are provided in a conductive region of the opposite conductivity type provided on a semiconductor substrate of one conductivity type, and a gate is made to face a channel region formed between the source region and the drain region. 1. A semiconductor device, wherein the impurity concentration of the channel region set in the conductive region is made different from the impurity concentration of the conductive region other than the channel region.
(2)半導体基板にチャンネル領域となる部分を遮蔽し
て不純物の拡散またはイオン注入により半導体基板とは
反対導電型の導電領域を形成し、チャンネル領域の不純
物濃度を制御することを特徴とする半導体装置の製造方
法。
(2) A semiconductor characterized by controlling the impurity concentration of the channel region by shielding a portion of the semiconductor substrate that will become the channel region and forming a conductive region of the opposite conductivity type to that of the semiconductor substrate by impurity diffusion or ion implantation. Method of manufacturing the device.
JP60071470A 1985-04-04 1985-04-04 Semiconductor device and its manufacture Pending JPS61229367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60071470A JPS61229367A (en) 1985-04-04 1985-04-04 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60071470A JPS61229367A (en) 1985-04-04 1985-04-04 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS61229367A true JPS61229367A (en) 1986-10-13

Family

ID=13461522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60071470A Pending JPS61229367A (en) 1985-04-04 1985-04-04 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS61229367A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4975288A (en) * 1972-11-22 1974-07-19
JPS549589A (en) * 1977-05-05 1979-01-24 Centre Electron Horloger Ic using complementary mos transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4975288A (en) * 1972-11-22 1974-07-19
JPS549589A (en) * 1977-05-05 1979-01-24 Centre Electron Horloger Ic using complementary mos transistor

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