JPS61239U - 超高周波回路基板のろう付け構造 - Google Patents

超高周波回路基板のろう付け構造

Info

Publication number
JPS61239U
JPS61239U JP1984084489U JP8448984U JPS61239U JP S61239 U JPS61239 U JP S61239U JP 1984084489 U JP1984084489 U JP 1984084489U JP 8448984 U JP8448984 U JP 8448984U JP S61239 U JPS61239 U JP S61239U
Authority
JP
Japan
Prior art keywords
circuit board
metal base
ultra
high frequency
frequency circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984084489U
Other languages
English (en)
Inventor
守 田原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1984084489U priority Critical patent/JPS61239U/ja
Publication of JPS61239U publication Critical patent/JPS61239U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/334—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は本考案の一実施例で分離斜視図に示し、第２図
は第１図のＡ−Ａ線載置状態側断面、第３図は本考案の
異なる実施例の分離斜視図、第４図は第３図のＣＣ線載
置状態側断面。 図において１は回路基板、２，４は金属基台、２１，４
１は凹部、３，５は低温ろう薄板、３１は突起、４２は
凹穴、５１は突起をそれぞれ示す。

Claims (3)

    【実用新案登録請求の範囲】
  1. （１）金属基台と、該金属基台の所定位置に固着される
    超高周波回路基板と、該金属基台と回路基板との間に介
    在しそれらを固着するための該回路基板の外形よりも小
    形な低濾ろう薄板を配置する構成であって、該金属基台
    と低温ろう薄板とは相互に位置決め手段を備えたことを
    特徴とする超高周波回路基板のろう付け構造。
  2. （２）位置決め手段は金属基台に形成された凹部または
    貫通孔と、低温ろう薄板に形成された該金属基台の凹部
    または貫通孔と嵌合する突起とからなることを特徴とす
    る実用新亭登録請求の範囲第１項に記載の超高周波回路
    基板のろう付け構造。
  3. （３）位置決め手段は金属基台に形成された回路基板を
    嵌合して位置決めするための枠状部と低温ろう薄板の周
    囲に形成された該枠状部に接する如き突起からなること
    を特徴とする実用新案登録請求の範囲第１項に記載の超
    高周波回路基板のろう付け構造。
JP1984084489U 1984-06-07 1984-06-07 超高周波回路基板のろう付け構造 Pending JPS61239U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984084489U JPS61239U (ja) 1984-06-07 1984-06-07 超高周波回路基板のろう付け構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984084489U JPS61239U (ja) 1984-06-07 1984-06-07 超高周波回路基板のろう付け構造

Publications (1)

Publication Number Publication Date
JPS61239U true JPS61239U (ja) 1986-01-06

Family

ID=30634047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984084489U Pending JPS61239U (ja) 1984-06-07 1984-06-07 超高周波回路基板のろう付け構造

Country Status (1)

Country Link
JP (1) JPS61239U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007012761A (ja) * 2005-06-29 2007-01-18 Tdk Corp 半導体ｉｃ内蔵基板及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007012761A (ja) * 2005-06-29 2007-01-18 Tdk Corp 半導体ｉｃ内蔵基板及びその製造方法

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