JPS61245645A - Signal separation circuit for multiplex converter - Google Patents

Abstract

PURPOSE:To separate signals of plural channel converting parts by providing an elastic store memory, plural shift registers, an elastic store memory control circuit and a shift register clock control circuit. CONSTITUTION:The multiplex signal output of an elastic store memory 1 which underwent the phase synchronization is supplied in common to the inputs of shift registers 31-35. Then the write clocks are applied to these registers 31-35 with a time shift respectively. Thus the signals equal to the prescribed bits are separated and stored in an idle time slot of an inter-channel interface of the shift registers. Then the read clocks of common prescribed bits are applied to the shift registers in a read mode. Thus the separated signals are outputted to the following channel converting parts respectively.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a signal separation circuit for a multiplex conversion device.

[Background of the invention]

In the signal separation circuit of the conventional PCM multiplex converter,
When RAM is used as the memory, an address counter for controlling reading and writing of the RAM, a selector for selecting the address for reading and writing, and a shift register corresponding to each channel converter are required, which increases the circuit scale. In addition, when using elastic store memory, the circuit size can be made smaller than when using RAM, but if used for each channel converter, elastic memory is expensive, so it is more expensive than when using RAM, and the memory size is also smaller. In addition to lower usage rates.

There were problems such as the need for a circuit to control the elastic memory corresponding to each channel converter. This type of PCM multiplex conversion device is described in, for example, NBC Technical Report Vol. 35. No. 12/19821 "PCM multiplex converter" [Object of the Invention] The object of the present invention is to solve the problems of the prior art described above, and to
An object of the present invention is to provide a signal separation circuit for a multiplex conversion device which separates signals of five channel conversion units using 256bLχ elastic memories or the like and reduces the circuit scale.

[Summary of the invention]

The present invention comprises one elastic store memory, a plurality of shift registers corresponding to a plurality of next-stage channel converters, an elastic memory control circuit, and a shift register clock control circuit. By inputting the phase-synchronized multiplexed signal output of the stick store memory in common to the inputs of the plurality of shift registers, and applying write clocks to the plurality of shift registers in a time-shifted manner, the shift registers The predetermined bits are separated and stored once during the idle time throttle of the channel-to-channel interface, and then separated to the next stage channel conversion section by giving a read clock of a common predetermined pit to the shift register at the time of readout. This is a signal separation circuit of a multiplex converter that outputs signals individually.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

FIG. 1 is a block diagram showing an embodiment of a signal separation circuit of a multiplex conversion device according to the present invention. In FIG. 1, this signal separation circuit includes a 256bLi elastic storage memory (256zs) 1 that inputs multiplexed signals from highway HWIN and performs phase synchronization, a control circuit 2 of the elastic store memory 1, and a control circuit 2 of the next stage. Five 4 bLi shift registers 5 provided corresponding to each of the five channel converters
1 to 35, and a quack control circuit 4 for the shift registers 51 to 55.

2 is an elastic store memory control time chart of FIG. 1, and FIG. 3 is a signal separation time chart of FIG. 1. Next, see Figure 2.3.

The operation shown in FIG. 1 will be explained with reference to FIG. In FIG. 2, 6 frames F1 to F7 of the 8 multiframes FO to F7 of the multiplexed signal data of the Eway HWR in FIG.
The multiplexed data (hatched portion) at a specific time of 6 is written into the elastic store memory 1 by the write IJ set W1 of the control circuit 2. Tonosai light reset W
R is applied only once to 8 multi-frames FO to F7, so if the data is 20 hLi per frame, 2
0X6=120 addresses are written. On the other hand, for reading, a read reset n is applied to each data at a specific time, and 120 addresses are read. This read memory content is rewritten every 8 multiframes. Next, in FIG. 6, the phase-synchronized serial output data read from the elastic store memory 1 of FIG. 1 is output as a serial signal of data BLK1 to 13LK5 of the 5-channel converter for each JhLi. Therefore, 4 is added to the data BLK1 to BLK5 of the 5-channel converter for each J hLi.

High-speed clock C for 4 clocks of corresponding time
K1 to CK5 are 5 corresponding to the next stage 5 channel conversion section.
When input from the clock control circuit 4 to the 4hLi shift registers 31 to 35, these high speed clocks CK1 to
By CK5, data B for 4 hLi of the corresponding next-stage 5-channel converter is generated during the free time throttle between the channel interfaces of shift registers 31 to 35.
LK1 to BLK5 are accumulated. At this time, invalid data is output by these clocks GK1 to CK5, but this time can be ignored since it is an empty time slot of the inter-channel interface. Next, 41rL beauty data BLK accumulated in these five shift registers 61 to 35
The data of data of 1 to BLK5 is simultaneously connected to the jig/nulling signal line GR1 to each of the 5 channel conversion sections by the low-speed read clocks GK1 to ClC5 of the clock control circuit 6.
~day IGR517) is output as data. By repeating this operation six times in one frame, multiplexed data for 24 channels can be separated for each channel converter.

As described above, according to this embodiment, in the signal separation circuit of the common part of the PCM multiplex converter, there is only one instead of using five expensive 256bLi elastic store memories, one for each of the five channel converters. There is no need to increase the circuit size.

〔Effect of the invention〕

As described above, according to the signal separation circuit of the multiplex conversion device of the present invention, one elastic store memory can perform signal separation of a plurality of channel conversion sections, and the circuit scale can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the signal separation circuit of the multiplex conversion device according to the present invention, FIG. 2 is the elastic store memory control time chart of FIG. 1, and FIG. 3 is the signal separation time of FIG. 1. It is a chart. 1... Elastic store memory 2... Its control circuit 61-35... Shift register 4... Its clock control circuit.

Claims (1)

[Claims] one elastic store memory that once accumulates and phase-synchronizes multiplexed signal input to a plurality of channel converters in the next stage and then outputs the same; a memory control circuit that controls writing and reading of multiplexed signals in the memory; A plurality of predetermined bit shift registers are provided corresponding to the plurality of channel converters in the next stage and commonly input the multiplexed signal output of the memory, and the multiplexed signal output to the plurality of shift registers. By applying the write clocks of the registers in a time-shifted manner, the signals of the corresponding predetermined bits are separated and once accumulated during the idle time throttle of the inter-channel interface of the register, and then a common read clock of the predetermined bits is provided. This is a signal separation circuit of a multiplex conversion device, which is composed of a register clock control circuit that outputs each signal to a channel conversion section in the next stage.