JPS6125218B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit configuration using complementary MOS transistors.

The present invention relates to a circuit configuration of a complementary MOS transistor formed by a self-alignment method using polysilicon as a gate material and a wiring material.

Conventionally, in the circuit configuration of polysilicon MOS transistors, when the drains of P-channel transistors and N-channel transistors are formed from polysilicon, PN junctions are formed in the wiring polysilicon due to diffusion by the self-alignment method. , which was extremely problematic in terms of circuit configuration.

This will be explained using FIGS. 1 and 2.

In FIG. 1, 11, 12, and 13 are respectively the sources and gates of P-channel transistors.
16, 17, and 18 indicate the drain, gate, and source of N-channel transistors. Reference numeral 14 denotes a drain-drain wiring, which is in direct contact with the drains 13 and 16. 12, 14, and 17 are made of polysilicon.

A circuit of this pattern is shown in FIG. As shown in FIG. 2, a diode 23 will be formed between transistors 21 and 22. this is,
If the forward breakdown voltage of the diode is ignored, there is no problem with its operation as an inverter.

However, if the circuit is configured in this way, a problem will occur in the circuit as shown in FIG.

FIG. 3 shows inverters connected in two stages. FIG. 4 is a pattern diagram of FIG. 3.

409, 410, 411, and 412 are formed of polysilicon. It can be seen that diodes 35, 36, and 37 in FIG. 3 are formed from the positions of the PN diffusion boundaries. As can be seen at a glance from FIG. 3, charging and discharging of the gates of the 34 N-channel transistors becomes impossible, and the circuit ceases to operate. In this way, when polysilicon is used for the drain-drain connection, it is impossible to construct a circuit with the configuration shown in FIG. 4.
Conventionally, in order to avoid this, polysilicon was used as the gate material, but the circuit was constructed using metal for the wiring. However, this method has many problems, including the inability to increase the degree of integration because it requires contact between metal and polysilicon, and the need for additional manufacturing steps.

The present invention is a method of configuring a MOS transistor circuit devised for the purpose of eliminating such drawbacks, reducing manufacturing steps, and providing a circuit configuration that can be highly integrated.

One embodiment of the present invention is shown in FIG. 5, and the present invention will be explained using this. In Figure 5, 50
1, 504, 505, and 508 each indicate a source, and 502, 503, 506, and 507 each indicate a drain. 510 and 511 are gates, and 512 and 513 are gates or wirings. Here, 510, 511, 512, and 513 are polysilicon. As can be seen from the pattern diagram in FIG. 5, in the present invention, the wiring is connected to the gate of the P channel from the P side of the drain-drain connection in the previous stage, and the wiring is connected to the gate of the N channel from the N side. It is something to do. This circuit is shown in FIG. In the present invention, as can be seen from FIG. 6, the inconvenience that occurred in FIG. 3 does not occur.

Furthermore, it is easy to see that such a pattern configuration can be applied not only to an inverter circuit as shown in FIG. 6, but to any circuit, and will not cause any trouble on the circuit. As an example, FIG. 7 shows the connection between two inverters and a NAND circuit. Each part in FIG. 7 can be easily inferred from FIGS. 4 and 5, and will not be explained here.

The present invention enables drain-to-drain connection using polysilicon, which was thought to be impossible in the past, and prevents the pattern area from increasing due to the conventional metal-polysilicon contact, and simplifies the process. Many effects can be expected, such as improved yield.

As described above, the present invention is a silicon gate
Regarding the circuit configuration of MOS transistors, it has become possible to use polysilicon for drain-drain connections, and the P side and N side can be connected with the smallest line and space of polysilicon, making it possible to greatly improve the degree of integration. The pattern configuration and circuit configuration are as follows.

[Brief explanation of the drawing]

Figures 1 and 2: Inverter pattern and circuit. Figures 3 and 4: Pattern and circuit of two-stage inverter. FIGS. 5 and 6: Pattern and circuit of a two-stage inverter according to the present invention. 7th
Figure: A pattern diagram of two inverters and a NAND gate according to the present invention.

Claims (1)

[Claims] 1. An inverter in which polysilicon is used as a gate material and a wiring material, and the drains of a first P-channel MOS transistor and a first N-channel MOS transistor are connected to each other, and the inverter is connected to the output side of the inverter, and the gates are commonly connected. In the MOS transistor circuit, the drains of the inverters are connected to each other through the drains of the first P-channel MOS transistor. P-type polysilicon as wiring and N as lead wiring from the drain of the first N-channel MOS transistor.
type polysilicon is directly connected to the gate of the second P-channel MOS transistor of the next stage circuit.
It is connected by P-type polysilicon as a lead wiring from the drain of the MOS transistor, and is connected to the second N channel of the next stage circuit.
A MOS transistor circuit characterized in that the gate of the MOS transistor is connected to the gate of the first N-channel MOS transistor by N-type polysilicon as a lead-out wiring from the drain of the first N-channel MOS transistor.